NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


2005 MAPLD International Conference

Ronald Reagan Building and International Trade Center
Washington, D.C.

September 7-9, 2005

Session L: Mitigation Methods for Reprogrammable Logic
in the Space Radiation Environment

Ken LaBel, NASA Goddard Space Flight CenterMike Wirthlin, Brigham Young University
Session Chairs:
Ken LaBel, NASA Goddard Space Flight Center
Mike Wirthlin, Brigham Young University

Session L will feature a lively discussion about mitigation methods for the application of reprogrammable devices in the space radiation environment.  The trade space of complexity, circuit impacts, verification, overhead in resources such as space and power, etc. versus effectiveness will be examined and discussed.  This workshop, held in both 2003 and 2004, will be continued this year in an expanded format.

Session L will held in the Hemisphere  B room and consist of two segments:

 

Wednesday, 4:05 to 5:35 pm

4:05 pm   Session Introduction
4:15 pm   Submission 175
"The Continuing Impact of Design and Process Hardening on the NSEU Sensitivity of Advanced CMOS PLD Technologies"
Joe Fabula, Austin Lesea, and Ray Matteis
Xilinx, Inc.
Abstract: fabula_a_.html
Presentation: fabula_p.pdf,   fabula_bof-l.ppt
4:27 pm   Submission 213
"Partial Evaluation Based Redundancy for Single Event Upset Mitigation in Combinational Circuits"
Sujana Kakarla and Srinivas Katkoori
University of South Florida
Abstract: kakarla_a.doc
Presentation: kakarla_p.ppt,   katkoori_bof-l.ppt
4:39 pm   Submission 201
"Single Event Effects Experimentation and Validation Techniques for SEU Mitigation Methods for Static Latch Based FPGAs"
Carl Carmichael1, Gary Swift2, Jeffrey George3, and Sana Rezgui1
1
Xilinx, Inc.
2JPL/Caltech
3Aerospace Corp.
Abstract: carmichael_a.html
Presentation: carmichael_bof-l.ppt
4:52 pm   Submission 204
"Reduced Triple Modular Redundancy for Tolerating SEUs in SRAM-based FPGAs"
Kamakoti Veezhinathan1, Sk. Noor Mahammad1, V. Muralidaran1, Vijaykrishnan Narayanan2, and Vikram Chandrasekhar1
1Indian Institute of Technology
2Pennsylvania State University
Abstract: veezhinathan_a.html
Presentation: kama_p.ppt,   kama_bof-l.ppt
Paper: kama_paper.pdf
5:04 pm   Submission 194
"SEU Mitigation in Re-Configurable FPGAs: Picking the Right Tool for the Job"
Brendan Bridgford and Carl Carmichael
Xilinx Inc.
Abstract: bridgford_1_a.html
Presentation: bridgford_p.ppt,   bridgford_bof-l.ppt
     
5:16 pm   Submission 146
"Virtex-II Pro PowerPC SEE Characterization Test Methods and Results"
David J. Petrick1, Wesley A. Powell1, Kenda S. Conklin1, Kenneth A. LaBel1 and Dr. James W. Howard2
1NASA Goddard Space Flight Center
2Jackson & Tull Chartered Engineers
Abstract: petrick_a.html
Presentation: petrick_p.ppt,   petrick_bof-l.ppt
Paper: petrick_p.doc

 


Thursday, 4:30 to 5:00 pm

4:30 pm   Submission 125
"Reconfigurable Processing Module"
Kevin Somervill1, Robert F. Hodson1, John Williams2, Robert Jones3
1
NASA LaRC, Hampton, VA
2University of Queensland, Brisbane, AU
3
ASRC Aerospace Corp., Greenbelt, MD
Abstract: somervill_a.html
Presentation: somervill_p.ppt,   somervill_bof-l.ppt
4:40 pm   Submission 173
"Upset Susceptibility and Design Mitigation of PowerPC405 Processors Embedded in Virtex II-Pro FPGAs"
Gary Swift1, Gregory Allen1, Jeffrey George2, Sana Rezgui3, and Carl Carmichael3, and Fayez Chayab4
1
JPL/Caltech
2The Aerospace Corporation
3Xilinx Corporation
4MDRobotics
Abstract: swift_1_a.html
Presentation: swift_p.ppt,   swift_bof-l.ppt
4:50 pm   Submission 1024
"Design of a ‘Single Event Effect’ Mitigation Technique for Reconfigurable Architectures"
Sajid Baloch1,2, Tughrul Arslan1,2, Adrian Stoica1,3
1University of Edinburgh
2Institute for System Level Integration, The Alba Campus, The Alba Centre
3NASA Jet Propulsion Laboratory
Abstract: 1024_baloch_a.pdf
Presentation: baloch_p.ppt,   baloch_bof-l.ppt

 

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