"Virtex-II Pro PowerPC SEE Characterization Test Methods and Results"

David J. Petrick1, Wesley A. Powell1, Kenda S. Conklin1, Kenneth A. LaBel1 and Dr. James W. Howard2
NASA Goddard Space Flight Center
2Jackson & Tull Chartered Engineers


The Xilinx Virtex-II Pro is a platform FPGA that embeds multiple microprocessors within the fabric of an SRAM-based reprogrammable FPGA.  The variety and quantity of resources provided by this family of devices make them very attractive for spaceflight applications.  However, these devices will be susceptible to single event effects (SEE), which must be mitigated.  

Observations from prior testing of the Xilinx Virtex-II Pro suggest that the PowerPC core has significant vulnerability to SEEs.  However, these initial tests were not designed to exclusively target the functionality of the PowerPC, therefore making it difficult to distinguish processor upsets from fabric upsets. The main focus of this paper involves detailed SEE testing of the embedded PowerPC core.  Due to the complexity of the PowerPC, various custom test applications, both static and dynamic, will be designed to isolate each unit of the processor.  Collective analysis of the test results will provide insight into the exact upset mechanisms of the PowerPC.  With this information, mitigations schemes can be developed and tested that address the specific susceptibilities of these devices.

The test bed will be the Xilinx SEE Consortium Virtex-II Pro test board, which allows for configuration scrubbing, design triplication, and ease of data collection. Testing will be performed at the Indiana University Cyclotron Facility using protons of varying energy levels and fluencies.  This paper will present the detailed test approach along with the results.


2005 MAPLD International Conference Home Page