"Reduced Triple Modular Redundancy for Tolerating SEUs in SRAM-based FPGAs"

Kamakoti Veezhinathan1, Sk. Noor Mahammad1, V. Muralidaran1, Vijaykrishnan Narayanan2, and Vikram Chandrasekhar1
1Indian Institute of Technology
2Pennsylvania State University


This paper proposes an optimized technique for SEU immunity in an SRAM-based FPGA through reduced Triple Modular Redundancy. The focus of the technique is on the Lookup-table network obtained from a gate-level netlist through a standard technology mapping tool. Instead of introducing redundant gates, we introduce redundant LUTs in the LUT network. The initution behind this strategy is that sensitive as well as insensitive gates are both absorbed into Look-up tables during the technology mapping stage. This idea is supported by the observation that most of the changes caused by SEUs in the inputs of an LUT are masked within the LUT itself. This leads to several insensitive LUTs in an LUT network, which absorb the SEU effects at each level of the network. Moreover, a sensitive LUT whose fanouts are all insensitive LUTs becomes a pseudo-insensitive LUT and hence need not be triplicated. The proposed technique was applied to 15 of the largest MCNC benchmark circuits and the hardened circuits were placed and routed using the Versatile Place and Route tool. The required additional redundancy is found to be only 38.57% of the original circuit compared to the 200% extra redundancy required by standard TMR techniques. This cost is further reduced by coupling logic simulation with the optimization technique at the expense of computational time. The extensive SEU fault simulation focuses on the actual SEU faults in FPGAs such as net disconnections, bridges, LUT bit changes and CLB input pin misconfigurations apart from soft errors. With nearly no loss of SEU tolerance, the proposed technique reduces the cost of a hardened circuit to nearly 46% of the cost of a standard TMR circuit.

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