"Upset Susceptibility and Design Mitigation of PowerPC405 Processors Embedded in Virtex II-Pro FPGAs"

Gary Swift1, Gregory Allen1, Jeffrey George2, Sana Rezgui3, and Carl Carmichael3, and Fayez Chayab4

1JPL/Caltech
2The Aerospace Corporation
3Xilinx Corporation
4MDRobotics

 

Abstract

Upsets in the configuration memory of reconfigurable FPGAs typically dominate over upsets of design level memory elements; however, mitigation techniques based on the combination of configuration scrubbing and tailored triple modular redundancy (TMR) in the design are able to reduce the effects of upsets. With the release of TMRTool, even the tedious job of changing a single-string design into a TMR-ed one can be largely automated. A by-product of TMR is that design-level memory elements are also largely mitigated.

Unfortunately, this fortuitous result applies only to "soft core" elements and does not extend to "hard core" features, like clock resources, multipliers and embedded processors. When there are enough copies, these can be used at a higher (read less automated) design level in voted triplets. This clearly does not apply to the processors embbeded in Virtex II-pro FPGAs because there are, at most, two copies.

In this paper, we show recent results for the upset susceptibility of memory elements (like register cells) in the embedded PPC405s in the V2P40 FPGA. For critical flight designs, these upsets can dominate the system error rate so we have considered several techniques for implementing various levels of redundancy, including single-, dual- and triple-chip options. The results of this analysis imply that the dual-chip option has several key advantages and may be the optimum choice given the constraints.

 

2005 MAPLD International Conference Home Page