"Single Event Effects Experimentation and Validation Techniques for SEU Mitigation Methods for Static Latch Based FPGAs"

Carl Carmichael1, Gary Swift2, Jeffrey George3, and Sana Rezgui1

1Xilinx, Inc.
2JPL/Caltech
3Aerospace Corp.

Abstract

“Xilinx Triple Module Redundancy,” or XTMR, is an SEU mitigation technique and design methodology intended to remove all single points of failure within the configuration control cells and user logic elements, including those in the voting circuitry, as well as preventing the propagation of single event transients, by “triplicating” all inputs, outputs, logic, clock domains and voters. XTMR combined with autonomous configuration error detection and correct (“scrubbing”) provides a unique and reliable SEU mitigation method for static latch based FPGAs. However, verification of this mitigation method presents significant challenges for the experimenter in terms of cost and coverage.

SEU Mitigation techniques are generally developed under the supposition that the speed of error detection and correction is far greater than the orbital upset rate environment. Accelerated testing violates this assumption by accelerating the upset rate while circuit operation speeds remain constant. This presents a challenge for demonstration of on orbit behavior in a beam environment.

This paper presents the fundamental philosophy performing SEE testing and validation of XTMR and Scrubbing for SEU Mitigations. The demonstrated method provides detailed analysis of a mitigation method in an accelerated environment in order to extrapolate error rate estimates for orbital environments. Additionally, the SEE test analysis demonstrates that this combined SEU mitigation technique pushes the cross-section for functional error for any design in any orbit to at least one order of magnitude below the established cross-sections for device level Single Event Functional Interrupts (SEFI).

 

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