Reconfigurable Processing Module

Kevin Somervill1, Robert F. Hodson1, John Williams2, Robert Jones3

1NASA LaRC, Hampton, VA
2University of Queensland, Brisbane, AU
3
ASRC Aerospace Corp., Greenbelt, MD

Abstract

To accommodate a wide spectrum of applications and technologies, NASA’s Exploration Systems Missions Directorate has called for reconfigurable, modular technology. In response, Langley Research Center is leading a program entitled Reconfigurable Scalable Computing (RSC) that is centered on the development of FPGA-based computing resources in a stackable form factor. This paper details the architecture and implementation of the Reconfigurable Processing Module (RPM), which is the key element of the RSC system.

The RPM is an FPGA-based, space-qualified Printed Circuit Assembly leveraging terrestrial/commercial design standards into the space applications domain. The form factor is similar to, and backwards compatible with, the PCI-104 standard utilizing only the PCI interface. The size is expanded to accommodate the required functionality while still better than 30% smaller than a 3U CompactPCI™ card and without the overhead of the backplane. The architecture is built around two FPGA devices, one hosting PCI and memory interfaces, and another hosting mission application resources; both of which are connected with a high-speed data bus. The PCI interface FPGA provides access via the PCI bus to onboard SDRAM, flash PROM, and the application resources—both configuration management as well as runtime interaction. The reconfigurable FPGA, referred to as the Applications Host FPGA—or simply “the application”—is a radiation-tolerant Xilinx Virtex-4 FX60 hosting custom application specific logic or soft microprocessor IP. The RPM implements various SEE mitigation techniques including TMR, EDAC, and configuration scrubbing of the reconfigurable FPGA. Prototype hardware and formal modeling techniques are used to explore the performability trade space. These models provide a novel way to calculate quality-of-service performance measures while simultaneously considering fault-related behavior due to SEE soft errors.

 

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