"The Continuing Impact of Design and Process Hardening on the NSEU Sensitivity of Advanced CMOS PLD Technologies"

Joe Fabula, Austin Lesea, and Ray Matteis
Xilinx, Inc.


This past year Xilinx continued its studies verifying, and more importantly quantifying the logic sensitivity of advanced sub-micron static-latch based FPGAs and PLDs to the effects of accelerated and natural (real world) atmospheric neutron environments. The effects of both the accelerated and natural neutron environments on various technologies (ranging from 220 nm CMOS down to and including multiple foundry sources of 90 nm CMOS) have been evaluated. Comparisons with data taken and published by other independent researchers on some of these same technologies is presented. A comparison of the effects of design and process hardening, particularly on 90 nm technologies from multiple silicon foundries, is detailed.

Additionally the effect of accelerated sources of atmospheric spectrum neutrons on the static latch storage cells in a number of flash-based products (including an ISP PROM and two generations of CPLD parts) have been concluded. The data presented includes the effect of a novel methodology of truncating the charge cloud that results from the neutron induced charged spallation products passing through the silicon lattice.

Measurements of the critical neutron per-bit cross sections of the storage elements of a select number of families of static latch based FPGAs, encompassing the range of 50,000 gate density devices (fabricated in a 220 nm five layer metal CMOS technology and operating at 2.5 volts) to 10,000,000 gate density devices (fabricated in 90 nm 9 to 11 metal layer CMOS technologies and operating from 1.0 to 1.2 volts) have been made. Data will be presented on the measured per bit proton and the per bit neutron cross sections of these same devices. Proton cross sections were measured using the Crocker Nuclear Laboratories Cyclotron (at 63 MEV) and using the University of Indiana Cyclotron Facility (over the range of 50-200 MEV). Critical bit neutron cross section data will also be presented on these technologies, taken utilizing the Hess spectrum of spallation neutrons available at the LANSCE facility of Los Alamos National Laboratories.

Then, the results of true atmospheric neutron exposure (of multiple technology levels) of a very large number of such devices (the total number of exposed latches exceeded 1.9 gigabits at each test implementation, and the tests were operated for periods of over one year) at four elevations (sea level, 5,000 feet 12,000 feet and 13,500 feet) will be presented, and this data will be used to calibrate the accelerated test methodologies and to quantify the apparent energy distributions and the altitude multiplier(s) of the resultant neutron flux. An attempt will be made to explain the deviation from the accepted practice of the neutron flux versus altitude as demonstrated at differing technology levels. Additional plans to expose these parts at even higher (aircraft) altitudes and to quantify the resulting neutron flux acceleration and energy distribution versus altitude will be discussed. The subject of NSEL (Neutron-induced Single Event Latch) will also be addressed for these technologies.

Finally, the calculation methodology used to assess the logic MTBF of these devices will be presented, along with a tabulation of the MTBFs of several devices at various altitudes and latitudes in support of terrestrial and avionics applications. Data will separate the effect of latch upset on programmed logic versus the impact on the accompanying BRAMs provided in these devices. Data supporting this methodology by various other researchers will be cited, along with the software development work on a tool dedicated to quantifying this factor for specific customer logic implementations in static latch-based FPGAs.


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