NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


2005 MAPLD International Conference

Ronald Reagan Building and International Trade Center
Washington, D.C.

September 7-9, 2005

Session M: "Low Power Design"

Matthew French, Information Sciences Institute, University of Southern CaliforniaMike Wirthlin, Brigham Young University
Session Chairs:
Matthew French, University of Southern California's Information Sciences Institute
Mike Wirthlin, Brigham Young University

Session M will be in an informal workshop format and will be open to all MAPLD attendees. This is the first year for this session and is being created based on interest from a number of MAPLD participants.

Session M will held in the Hemisphere  B room and consist of one  segment:

 

Thursday, 5:00 to 6:00 pm

5:00 pm   Introduction
5:05 pm   Submission 195
"High Performance Low Power Single Chip Reconfigurable Supercomputer for High-end Aerospace Applications"
N. Venkateswaran, M. Arvind, C. Karthik, G. Karthik, V. Vishwanath, and K. Viswanath
Waran Research Foundation
Abstract: venkateswaran_a.html
Presentation: nagarajan_p.ppt,   nagarajan_bof-m.ppt
Paper: nagarajan_paper.pdf
5:15 pm   Submission 197
"An Ultra Low Power Reconfigurable Task Processor for Space"
Brian Smith1, Greg Alkire1, and Wes Powell2
1
PicoDyne Inc.
2NASA Goddard Space Flight Center
Abstract: smith_a.html
Presentation: smith_p.ppt
5:25 pm   Submission 138
"High Performance, Radiation Hardened, Ultra Low Power Space Computer Leveraging COTS Microelectronics with SEE Mitigation"
David R. Czajkowski, David J. Strobel, et. al.
Space Micro Inc.
Abstract: czajkowski_1_a.html
Presentation: czajkowski_p.ppt,   czajkowski_bof-m.pdf
5:35 pm   Submission 1013
"A Novel Time- Area-Power Efficient Single Precision Floating Point Multiplier"
Himanshu Thapliyal and M.B Srinivas
International Institute of Information Technology
Abstract: thapliyal_3_a.html
Presentation: thapliyal_p.ppt,   thapliyal_bof-m.ppt
5:45 pm   Submission 207
"Integrated Tool Suite for Post Synthesis FPGA Power Consumption Analysis"
Matthew French1, Li Wang1, Tyler Anderson2, Michael Wirthlin2
1
University of Southern California, Information Sciences Institute
2Brigham Young University
Abstract: french_a.html
Presentation: french_p.ppt,   french_bof-m.ppt
     
5:55 pm   General Discussion

 

2005 MAPLD International Conference Home Page


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