"Integrated Tool Suite for Post Synthesis FPGA Power Consumption Analysis"

Matthew French1, Li Wang1, Tyler Anderson2, Michael Wirthlin2

1University of Southern California, Information Sciences Institute
2Brigham Young University


For many FPGA platforms, such as space-based, handheld, and micro-sensors, power has become a critical design parameter however, available FPGA synthesis and routing tools optimize for speed or area, but real-time power consumption optimization is rare. Even current COTS power estimation tools, the first step in achieving power optimization, are difficult to use and have limited utility to the FPGA design process. This paper will outlines the development of an FPGA Low-power Intelligent Tool Environment (LITE) , which seeks to address these issues and make power a first class design constraint.

The development of a more robust tool suite for exploring power consumption at the placed and routed circuit-level, will be discussed first. Extensions to an existing CAD tool infrastructure, JHDL, which allows full interoperability with COTS CAD tool flows and HDL languages will be discussed. These tools enable the capability to simulate and analyze power within the same tool environment, visualize instantaneous and cumulative power consumption over time, and cross probe power overlays with logical simulation information. A key contribution at this level though, is the ability to rapidly sort through and plot circuit power data in power (or capacitance) versus wire length, wire fanout, or number of Programmable Interconnect Points.

The creation of these tools enabled the development of power analysis tools at the post-synthesis level. The second section of the paper will focus primarily on the development and analysis of statistical and probabilistic wire capacitance prediction models necessary for accurate post-synthesis power estimation. This paper will explore models predicting wire capacitance as a function of fanout, and device utilization in terms of either number of components or number of wires utilized. Other models, such as data versus control are discussed. The fanout model was determined to be the most robust and accurate model, having a 4% per net mean error, 12% variance when compared against a placed and routed circuit using Xilinx’s Xpower tool. These tools allow an FPGA designer to more quickly determine if they are on budget to meet power specifications and rapidly explore the impact of high-level circuit design trade-offs.

The final section of the paper will discuss optimization tips discovered during this research and future plans for optimization tools. Tips covered will include things such as the Xilinx East-West vs North-South capacitance bias, unwanted antennas, and direct interconnect variance. The LITE tools seek to optimize a circuit for power by dropping in standard COTS timing and placement constraints into the User Constraint Files. The tools currently have the capability to rapidly create and experiment with these constraints. Preliminarily, we have demonstrated a 10-22% reduction in power utilization without affecting the functionality of a circuit and algorithms to fully automate this process are under development.

It is our conclusion that if existing COTS tools were to share relevant information integrated across different levels of the tool flow combined with a few enhancements such as statistical prediction modeling, power can become a first class design constraint, allowing improved power analysis and optimization.


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