"A Novel Time- Area-Power Efficient Single Precision Floating Point Multiplier"
Himanshu Thapliyal and M.B Srinivas
International Institute of Information Technology
In this paper, a Single Precision IEEE 754 floating-point multiplier with high speed and low power is presented. The Floating–point multiplication is similar to the integer multiplication as it involves the multiplication of the mantissa when represented in the sign magnitude form. In accordance to the single precision IEEE 754 standard the mantissa is of 24 bits, thus, the bottleneck of this design is the 24x24 bit integer multiplier. In order to circumvent this problem, Urdhava Triyakbhyam algorithm of ancient Indian Vedic Mathematics is utilized.
In the proposed architecture, the 24x24 bit multiplication operation is fragmented to four parallel 12x12 bit multiplication modules. The 12x12 multiplication modules are implemented using small 4x4 bit multipliers. Thus the whole 24x24 bit multiplication operation is divided into 36 4x4 multiply modules working in parallel. In the unsigned 24x24 bit multiplier architecture, four redundant 4x4 multiplier are provided to enforce the feature of self reparability. Each 4x4 redundant multiplier will take care of the fault in one of the 12x12 multiplier. The 12x12 multiplier is implemented using 9 4x4 multipliers ,therefore, if there is a fault in one of the 4x4 bit multipliers ,it abandons its output and replaces it by the one from the redundant multiplier assigned to the corresponding block of 12x12 multiply module. Power saving is attained as the 4x4 module that gives an erroneous result would be devoid of power supply .Otherwise, the corresponding redundant 4x4 multiplier will be switched off. The proposed architecture brings out the idea of reconfiguarability at runtime. This is possible when the mantissa is of 12 bits, which requires only one 12x12 multiplication block to be enabled through a control circuitry. While, the other three 12x12 multiplication blocks can be switched off during its computation, thus saving huge amount of power. Reconfiguarability at runtime can also be extended to 8 bit and 4 bit mantissa, thereby reducing the power consumption largely. The Urdhava Triyakbhyam utilized for multiplication has also made the testing of the circuit much easy. A novel testing method based on Urdhav Triyakbhyam has been proposed in the paper for testing the multiplier. The proposed exhaustive DFT technique greatly reduces the test vector length required to verify the data validity. The multiplier has been designed, optimized and implemented on an FPGA based system. A comparison between the results of the proposed design and previously reported is done. At the end, an optimized design and implementation of a floating-point adder/subtractor and accumulator has also been investigated. Thus, a highly regular, self-repairable floating point parallel multiplier architecture (which can be directly scaled for larger multipliers) along with DFT implementations is presented. Both the repairing and testing take the advantage of the efficient partitioning of the circuit inherent in the decomposition approach.
Keywords: Floating Point Multiplier, DSP, Arithmetic and Logical Unit.
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