"High Performance Low Power Single Chip Reconfigurable Supercomputer for High-end Aerospace Applications"

N. Venkateswaran, M. Arvind, C. Karthik, G. Karthik, V. Vishwanath, and K. Viswanath
Waran Research Foundation

Abstract

When it comes to aerospace applications power aware computing plays an important role. There is always a trade-o between the power consumed and the performance achieved. On the other hand, for on-board supercomputers, power as well as performance are of equal importance due to mission criticality of applications and hence no trade o is acceptable. In this paper, we present the capability of Memory In Processor Super Computer On a Chip (MIP SCOC)[1][2][3][4] to achieve sustained high performance consuming low power as against the PIM based ALU architectures employed in conventional supercomputing clusters. The unique feature of the MIP SCOC being the Algorithm Level Functional Units (ALFU) and the Algorithm level Instruction Set Architecture (ALISA), is greatly responsible for achieving very high ‘performance to power’ ratio. These varied class of algorithm level functional units are directly amenable for e cient FPGA based implementation over the ALU based node architectures. Through intensive simulation of synthetic applications (custom designed, involving widest class of algorithms) on emulated MIP SCOC, it is brought out that the power reduction is achieved by drastic cut down in the number of memory accesses. It is shown as a case study that the ‘peak performance to power’ ratio of a single MIP SCOC is much higher compared to IBM Blue Gene cluster employing 1300 POWER PC processing nodes. Such compaction of high performance and low power aspects onto a single chip reduces the size of the on-board supercomputer to a large extent.

References

  1. N Venkateswaran, Arrvindh Shriraman, and S. Niranjan Kumar. Memory in processor supercomputer on a chip processor design and execution semantics for massive single chip performance. Fifth Workshop on Massively Parallel Processing (WMPP), IPDPS, 2005.
  2. N. Venkateswaran, Aditya Krishnan, Niranjan Soundarajan, and Arrvindh shriraman. Memory in processor : A novel design paradigm for supercomputing architectures. ACM SigArch Computer Architecture News, June 2004.
  3. N. Venkateswaran, B. Aravindakshan, R. Prem Kumar, N. Sivaramakrishnan, and G. Sudharsan. Simultaneous multiple algorithm execution : Sustaining teraops in a mip scoc node. Submitted to HiPC 05 Paper ID.1568962773, 2005.
  4. N. Venkateswaran, Arvind M, Karthik C, Karthik G, Vishwanath V, and Viswanath K. Parallel mapping of simultaneous multiple applications (smapp) on multi-host hierarchical mip scoc cluster. Submitted to HiPC’05, 2005.
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