2006 MAPLD International Conference
Ronald Reagan Building and International Trade Center
with a session at the Smithsonian National Air and Space Museum
September 26-28, 2006
Session M: "Low Power Design"
Matthew French, University of Southern California's Information Sciences Institute
Mike Wirthlin, Brigham Young University
Session M will be held on Wednesday, September 27, 2006 from 4:05 - 5:35 pm in Oceanic B.
"FPGA Implementation and Power Modeling of FWT for Pattern Recognition"
S. Chandrasekaran and A. Amira
"Low Power Optimisation of DSP Core Networks on FPGA for High End Signal Processing Systems"
Stephen McKeown, Scott Fischaber, Roger Woods, John McAllister and Eoin Malins
Queen’s University Belfast
"Algorithm Agile Low Power and High Data Rate Optimized System for RadHard Applications"
Syneren Technologies Corporation
"Multi-Level Parallelism for Power and Energy Aware Design – Verified Using Novel Functional Level Power Analysis & Modelling (FLPAM)"
Shrutisagar Chandrasekaran and Abbes Amira
Brunel University, London
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