"Multi-Level Parallelism for Power and Energy Aware Design Verified Using Novel Functional Level Power Analysis & Modelling (FLPAM)"

Shrutisagar Chandrasekaran and Abbes Amira
Brunel University, London


Parallelism as a technique [1] has been well exploited by processor manufacturers in recent times as a means of reducing the power consumption while maintaining competitive performance metrics. While the fabric of FPGA systems are fixed, power consumption of designs implemented on FPGA can also benefit from similarly exploiting the massive parallelism capabilities of commercial FPGAs. The viability of this approach for yielding energy and power efficient architectures by applying parallelism at various design levels is suitable demonstrated using various test-bench architectures.

As FPGA based systems scale up in complexity, energy aware designs with strict power budgets require the designer to have a reasonable estimate of the power consumed by various subsystems in the design early on in the design cycle itself [2]. In line with the industry trend of IP reuse and block/core based design techniques that are increasingly being used in multi-million gate FPGA based designs, a novel technique for the estimation and statistical modeling of parametrisable IP blocks, called Functional Level Power Analysis and Modelling (FLPAM) has been introduced.

The underlying concept is to build a mathematical model that incorporates all the system

variables, enabling the user to perform high level estimation of the power and energy metrics of the core for a given set of parameters early on in the design cycle itself. The steps involved in building the power model are as follows:

  1. Create a power chart by measuring power for each individual component of dynamic power, i.e. signal, logic, clock, I/O;

  2. Identify all variables in the system, including user customisable ones, and internal system parameters, eg. frequency, vector length, area and voltage;

  3. Define empirical relationship between all the system variables; and

  4. Derive the coefficients for each individual power component by performing non-linear regression analysis on the data in power chart for fitting the system variables.

The usefulness of FLPAM in supplying the designers with priori knowledge of various system parameters and tradeoffs that are required to achieve energy and power budgets, especially in energy and thermally sensitive environments such as satellites cannot be overemphasized.

Examples of real world designs that have been implemented by exploiting extreme parallelism and fine-tuned using FLPAM are described in the full paper.


  1. [1] Chandrakasan, A. P., S. Sheng, and R. W. Brodersen, "Low-power Digital CMOS Design," IEEE Journal of Solid State Circuits, pp. 473-484, April 1992.

  2. [2] K. Poon, A. Yan, S.J.E. Wilton, ``A Flexible Power Model for FPGAs'', 12th International Conference on Field-Programmable Logic and Applications, Sept 2002


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