"FPGA Implementation and Power Modeling of FWT for Pattern Recognition"

S. Chandrasekaran and A. Amira
Brunel University

Abstract

In this paper we present a novel design for an efficient field programmable gate arrays architecture of fast Walsh transform for hardware implementation of pattern analysis techniques such as projection kernel calculation and feature extraction used in space applications when dealing with image analysis. The proposed architecture is based on distributed arithmetic principles using ROM accumulate technique and sparse matrix factorisation. The implementation has been carried out using a hybrid design approach based on Celoxica Handel-C which is used as a wrapper for highly optimised VHDL cores. The algorithm has been implemented and verified on the Xilinx Virtex-2000E FPGA. An evaluation has also been reported based on maximum system frequency and chip area for different system parameters, and has been shown to outperform existing work in all key performance measures. Additionally, a novel Functional Level Power Analysis and Modelling (FLPAM) methodology has been proposed to enable a high level estimation of power consumption.

Keywords: Walsh transform, field programmable gate array, pattern recognition, space applications, distributed arithmetic, Handel C, low power, energy aware, pipelining, parallelism, Optimisation, Modelling

 

2006 MAPLD International Conference Home Page