"Algorithm Agile Low Power and High Data Rate Optimized System for RadHard Applications"

Meg Vootukuru
Syneren Technologies Corporation


In typical hardware implementations the algorithm is fixed at the time of manufacturing. A problem can arise if the algorithm is "broken" and is no longer considered secure. In the case of malfunction (which is very likely due to process variations in ASICs), the devices would have to be redesigned and re-manufactured, presumably at high cost. In such cases, FPGAs/PLDs provide better alternative to ASICs. Also, in the case of crypto algorithms, there may be a case where the highly secretive information has been broken into. In such situations, it is very likely that one would want to change the algorithm or the "key" to the encrypt/decrypt algorithm. This is an example of the need for “algorithm agility”. On one hand, reconfigurable logic provides a hardware solution to algorithm agility. On the other hand, FPGA and PLD technology traditionally yields low data rate and is not power efficient.We present an innovative approach to algorithm agility based on reconfigurable hardware (FPGAs) co-processor architecture, while optimizing the design for high data rate and low-power and constrained with Radiation Hardness in the case of Space based applications.

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