NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


2005 MAPLD International Conference

Ronald Reagan Building and International Trade Center
Washington, D.C.

September 7-9, 2005

Session B. Logic Design and Processors
(Wednesday afternoon, September 7)


Keith Bergevin - Defense Microelectronics Activity (DMEA)Creigh Gordon - Air Force Research Laboratory/VSSE
Session Chairs:
Keith Bergevin - Defense Microelectronics Activity (DMEA)
Creigh Gordon - Air Force Research Laboratory/Space Vehicles Directorate/Space Electronics Branch

1:50 PM  

Submission 179
"Safe and Efficient One-Hot State Machine"
Jason Xin Zheng, Sunant Katanyoutanant, and Martin Le
Jet Propulsion Laboratory
Abstract: zheng_a.html
Presentation: zheng_p.ppt

2:15 PM  

Submission 170
"Verification of Moderate Complexity IP: Case Study, MIL-STD-1553B Interface"
Rod Barto
NASA Office of Logic Design
Abstract: barto_2_a.html
Presentation: barto_p.ppt,   barto_bof-w.ppt

2:40 PM  

Submission 241
"Accessible Formal Verification for Safety-Critical FPGA Design"
John Lach1, Scott Bingham1, Carl Elks1, Travis Lenhart1, Thuy Nguyen2, Patrick Salaun2
1
University of Virginia
2Electricité de France
Abstract: lach_a.html
Presentation: lach_p.ppt,   lach_bof-w.ppt

3:05 PM  

Submission 216
"Evaluation of Error Detection Strategies for an FPGA-Based Self-Checking Arithmetic and Logic Unit (ALU)"
Varadarajan Srinivasan, Julian Farquharson, William H. Robinson, and Bharat L. Bhuva
Vanderbilt University
Abstract: srinivasan_a.html
Presentation: srinivasan_p.ppt

3:30 PM  

BREAK in the Atrium Hall

4:05 PM BIRDS OF A FEATHER SESSION #1
5:35 PM  

Submission 150
"Scientific Computing in Space Using COTS Processors"
Jeremy Ramos. Roger Sowada, and David Lupia
Honeywell
Abstract: ramos_a.html
Presentation: ramos_p.ppt

6:00 PM  

Submission 212
"Configurable Soft Processor Arrays Using the OpenFire Processor"
Stephen Craven, Cameron Patterson, and Peter Athanas
Virginia Polytechnic Institute and State University
Abstract: craven_a.html
Presentation: craven_p.ppt
Paper: craven_p.doc

6:25 PM  

Submission 189
"Fixed and Floating Point for VHDL""
Jim Lewis1 and David Bishop2
1
SynthWorks Design Inc.
2Eastman Kodak
Abstract: lewis_a.html
Presentation: lewis_p.pdf,   lewis_p_bw.pdf

6:50 PM  

END DAY 1

 

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