"Verification of Moderate Complexity IP: Case Study, MIL-STD-1553B Interface"
NASA Office of Logic Design
This paper describes the steps taken to verify the electrical design of a 1553 IP core for spacecraft applications. Even though the core had passed a 1553 verification test, the fact that it meets the 1553 protocol requirements is no guarantee that the design is sufficiently robust for a spacecraft system. The techniques used in the electrical verification will be applicable to verification of other FPGA designs.
2005 MAPLD International Conference Home Page