"Configurable Soft Processor Arrays Using the OpenFire Processor"

Stephen Craven, Cameron Patterson, and Peter Athanas
Virginia Polytechnic Institute and State University


As transistor sizes shrink and interconnect delays relative to gate delays grow, designers are increasingly turning to single chip multiprocessor arrays to improve performance. Researchers have implemented multiprocessor systems in FPGAs [1][2] using configurable soft processors such as the Xilinx MicroBlaze. While soft processors can be configured for a specific application to maximize performance, no user editable HDL source exists for the MicroBlaze, limiting the configurability to a small set of options available through the Xilinx Embedded Development Kit (EDK). Fully configurable open source soft processor cores are available, such as the Leon and OpenRISC; however, neither approach the performance or user base of the MicroBlaze nor feature as impressive a toolset [3].

As a stepping-stone for our research into optimizing arrays of soft processors, we have created OpenFire, a soon-to-be-available configurable soft processor featuring a MicroBlaze-compatible instruction set. Unlike aeMB [4], a previous attempt at a clean room implementation of the MicroBlaze, OpenFire correctly executes code compiled for the MicroBlaze, features an optional hardware multiplier and Fast Simplex Link (FSL) buses, and is extensively documented. At a maximum speed of 100MHz in a Virtex II-Pro, the OpenFire scores 58.5 DMIPS on the Dhrystone 2.1 benchmark – a mere 1% less than a similarly configured MicroBlaze while using 12% fewer slices.

To demonstrate the benefits of configurable soft processor arrays, we implemented a median image filter using the OpenFire and compared the results to a MicroBlaze implementation. The OpenFire processor allows us to fully configure the array to the application, stripping out all unnecessary logic to permit more processors per FPGA while modifying the datapath width and the instruction set to match the application. For example, in our image filter implementation we reduced the slice utilization by 45% by shrinking the datapath width to 16 bits from 32 bits, allowing for a larger array of processors and higher overall performance. While the configurability of OpenFire can benefit multiple research domains, including reliable soft processors, our paper will focus on the performance and design time improvements that can be achieved through configurable processing arrays.


  1. James-Roxby, P., Schumacher, P., and Ross, C. “A Single Program Multiple Data Parallel Processing Platform for FPGAs,” 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’04).
  2. Clark, C., Nathuji, R., and Lee, H. “Using an FPGA as a Prototyping Platform for Multi-core processor Applications,” Workshop on Architecture Research using FPGA Platforms, 2005.
  3. Mattsson, D., and Christensson, M. “Evaluation of synthesizable CPU cores,” Master’s Thesis. Chalmers University of Technology, 2004.
  4. http://www.opencores.com/projects.cgi/web/aemb/overview


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