"Evaluation of Error Detection Strategies for an FPGA-Based Self-Checking Arithmetic and Logic Unit (ALU)"

Varadarajan Srinivasan, Julian Farquharson, William H. Robinson, and Bharat L. Bhuva
Vanderbilt University

Abstract

The detection of alpha-particle-induced soft errors in arithmetic and logic units (ALUs) poses a problem due to the difficulty in determining a unique association of the output to the set of inputs. Although several studies have addressed ASIC circuits, there has not been a detailed analysis of error detection strategies for ALUs implemented in an FPGA. Traditional radiation-hardening approaches use specialized circuit-level techniques suitable for ASIC markets, but not for FPGAs. However, if the ALUs are designed with built-in error detection logic, it could signal the need for reconfiguration of the FPGA. This paper will present a comparative study of coding strategies to detect single-bit soft errors in ALUs. The diverse set of operation types (arithmetic, logical, shift/rotate) presents a challenge for selecting a coding strategy. This paper will evaluate a global coding strategy for all ALU instructions versus separate coding strategies for groupings of ALU instructions. The Berger check prediction technique is used for the global coding strategy [1]. The instruction grouping strategy will combine a remainder check for arithmetic instructions and a parity check for logical and shift/rotate operations. A trade-off analysis of area versus performance will be shown for the ALUs designed using the selected coding techniques. The results will be useful to determine an efficient coding strategy based upon both the application and hardening requirements.

Reference

[1] J. C. Lo et al., “An SFS Berger check prediction ALU and its application to self checking processor designs,” IEEE Trans. on Computer Aided-Design, vol. 11, pp. 525-540, Apr. 1992.

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