Ronald Reagan Building and International Trade Center
September 8-10, 2004
Alan Hunsberger, National Security Agency
Douglas Fouts, Naval Postgraduate School
Thursday, September 9, Starting at 8:00 am
Session F will be in an informal workshop format and will be open to all MAPLD attendees. The session will be in two parts as detailed below.
Part 1 will consist of DARPA-like "Quad Chart" presentations on the reconfigurable computing related poster papers. These will be fast-moving presentations with each speaker having two minutes. An open Q&A session will follow for questions related to the quad charts or any other topic of interest.
Part 2 will be a panel session with five vendors of high performance reconfigurable computing machines:
- Cray, Inc. - Represented by Ron Westfall
- High Performance Technologies, Inc. - Represented by Chris Powell
- Silicon Graphics, Inc. - Represented by Steve Miller and Brian Larson
- SRC Computers, Inc. - Represented by Jon Huppenthal and Dan Poznanovic
- Star Bridge Systems, Inc. - Represented by Rebecca Krull and Bradley Alston.
Each vendor will have ten minutes for a presentation on their hardware and software (no questions from the audience). Following the five presentations, the floor will be open for audience questions. The questions will be addressed to all five vendors and each vendor will have up to two minutes to answer (as an example, a question might be "What commercial applications do you see as your market niche?")
Schedule for Session F
Part 1: Quad Charts and Open Q&A 8:00 am Quad Charts Presentations 8:30 am Open Q&A 9:15 am Break Outside the Amphitheater and Dedicated Poster Session. Part 2: Vendor Panel 10:00 am Presentations from five high performance reconfigurable computing machine vendors 10:50 am Q&A session with the vendors 12:00 pm Lunch In The Atrium Ballroom
Papers Anticipated for Discussion
"A Methodology for System-on-a-Programmable-Chip Resources Utilization"
Sin Ming Loo1 and Simon Y. Foo2
1 Boise State University
2 Florida A&M University Florida State University
Presentation: p194_loo_s.ppt, p194_loo_s.pdf
"Design and Analysis of Parallel N-Queens on Reconfigurable Hardware with Handel-C and MPI"
Vikas Aggarwal, Ian A. Troxel1, and Alan D. George
University of Florida
"Acceleration of Traffic Simulation on Reconfigurable Hardware"
Justin L. Tripp, Henning S. Mortveit, and Maya Gokhale
Los Alamos National Labs
"Graphical Design Environment for a Reconfigurable Processor"
Gregory Donohoe1, Tu Le1, David Buehler1, and Pen-Shu Yeh2
1 University of Idaho
2 NASA Goddard Space Flight Center
"Hardware-based Image Retrieval and Classifier System"
Jason C. Isaacs, Joe Petrone, and Simon Y. Foo
Florida A&M University - Florida State University
"Elliptic Curve Cryptography over GF(2m) on a Reconfigurable Computer: Polynomial Basis vs. Optimal Normal Basis Representation Comparative Study"
Kris Gaj, Sashisu Bajracharya, Chang Shu, Sang Han George Mason University
Tarek El-Ghazawi The George Washington University
"A Case Study in HW/SW Codesign and Project Risk Management: The Honeywell Reconfigurable Space Computer (HRSC)"
Jeremy Ramos1 and Ian A. Troxel2
1 Honeywell Space Systems Inc.
2 University of Florida
"A HW/SW Co-design Tool for Modern FPGA's with FPGA-Embedded Processors"
Jason Scott1, Ted Bapty1, Sandeep Neema1, Brandon Eames1, Andrew Vandivort2, Sarir Khamsi2, Troy Gangwer2
1 Vanderbilt University
"A Reconfigurable Computing Model for Biological Research Application of Smith-Waterman Analysis to Bacterial Genomes"
J. Yardley and K. Gilson
"An automated pipeline balancing in the SRC Reconfigurable Computer and its application to the RC5 cipher breaking"
Hatim Diab1, Miaoqing Huang1, Kris Gaj2, Tarek El-Ghazawi1, Nikitas Alexandridis1
1 The George Washington University
2 George Mason University
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