NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


The NASA ASIC Guide: Assuring ASICs for SPACE

Chapter Four: Perspective on Part Acceptance

We wish to alert ASIC development teams of several current trends in the integrated circuit industry that will significantly alter the procedures described earlier in this section. The first affects QML and QPL requirements.

QML and QPL state that if the vendor supplies sufficient data to show that the improvements in their fabrication process render certain screens unnecessary, the government may approve discarding those screens. However, it is expensive to generate enough data to show that the exclusion of a standard screening step does not adversely effect reliability and this is yet to be done. This practical reality tends to significantly delay deleting obsolete screens from QPL or QML programs. Vendors need to justify newly proposed methodologies by presenting well-correlated data to the TRB, for QML, or to Defense Electronics Supply Center (DESC), for QPL.

Also, blending the QML and QPL programs into a single program would have a major impact on military qualification. The QML program grew out of the early work on the QPL/S gate array program. Today these programs are very similar and it is likely that they may combine in the near future, at least for ASICs. The replacement program will probably look much more like QML than the traditional off- the-shelf QPL. For more information see the appendix "Government Qualification Programs".

The rapidly developing simulation tool industry provides another example of a technology trend that will impact qualification. As this industry becomes better at predicting parametric margins, it will reduce the need for engineering part margin characterization. Research is underway to establish the correlation between simulated and real- world margins and the causal relationships between process, simulation, and device characteristics. This research will lead to more accurate interpretations of simulation results and reduce or even eliminate the need for characterization. Other trends are also decreasing labor costs, such as "in-line" tests.

As some "end-of-line" tests become obsolete, new "in- line" tests are actively being developed. For example, applying visual inspection has approached practical limitations due to the vast number of components to inspect. As imaging and pattern matching develop, they may offer an alternative to visual inspection. Imaging and pattern matching can assess the metallization of each metal mask during the fabrication process, multiplying the effectiveness of today's visual inspection test. Visual inspection relies on the capability of the human eye, thus limiting the inspection to the top layer.

Improved testing methods coupled with increased understanding of their predictive powers also hold potential for decreasing labor costs. For instance, they will provide more inferences about the quality of metal lines without having to "look" at them. To this end, JEDEC is proposing an alternate to MIL-STD- 883, Method 2010 (visual inspection). Also, design- for-test concepts are revolutionizing part acceptance as ATPG methods, delay-fault testing, partial scan, and other testability methods develop.

A relatively new test method for detecting CMOS defects, called IDDQ testing, has particularly high promise for complementing or even replacing conventional stuck-at fault testing because of its simplicity and the possibility of lower development cost. However, the inability to work with GaAs devices limits IDDQ testing.

For current information on trends in part acceptance, contact JEDEC, Rome Laboratories or DESC.


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