NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


The NASA ASIC Guide: Assuring ASICs for SPACE

Acronyms

ASIC		application-specific integrated circuit
ATPG		automatic test pattern generation
BILBO		built-in logic block observation
BIST		built-in self-test
CAD		computer-aided design
CAE		computer-aided engineering
CAT		computer-aided testing
CDR		critical design review
CE		concurrent engineering
CMOS		complementary metal-oxide semiconductor
CPU		central processing unit
DESC		Defense Electronics Supply Center
DFT		design for test
DRC		design rule check
ECL		emitter-coupled logic
EDA		electronic design automation industry
EDAC		error detection and correction
EDIF		electronic design interchange format
ERC		electronic design augomation
FDL		fault detection and localization
FPGA		field-programmable gate array
GA		gate array
GaAs		gallium-arsenide
HDL		hardware description language
HOL		high-order logic
I/O		input/output
IEEE		Institute of Electrical and Electronics Engineers
JAN		Joint-Army-Navy
JEDEC		Joint Electron Device Engineering Council
JTAG		Joint Test Action Group
LCC		leadless chip carrier
LET		linear energy transfer
LFSR		linear feedback shift register
LSSD		level-sensitive scan design
LTPD		lot tolerance percent defective
NRE		nonrecurring engineering (charges)
PDA		percent defective allowable
PDR		preliminary design review
PG		pattern-generation (tape)
PGA		pin grid array
PM		parametric monitor
QCI		quality conformance inspection
QCRIT		critical charge
QML		Qualified Manufacturers List
QMP		Quality Management Plan
QPL		Qualified Products List
RAM		random access memory
ROM		read-only memory
RTL		register-transfer level
SC		standard cell
SEC		standard evaluation circuit
SEE		single-event effect
SEL		single-event latchup
SEU		single-event upset
SMD		standardized military drawing
SOI		silicon-on-insulator
SOS		silicon-on-sapphire
SOW		statement of work
SPC		statistical process control
SPICE		simulation program with IC emphasis
SRL		shift register latch
TAP		test access port
TCI		technology conformance inspection
TCV		technology characterization vehicle
TDDB		time-dependent dielectric breakdown
TID		total ionizing dose
TMT		triple modular redundancy
TQM		total quality management
TRB		technology review board
TRSL		test requirements and specification language
TTL		transistor-transistor logic
VHDL		VHSIC hardware description language
VHSIC		very high scale integrated circuit
VLSI		very large scale integration
WAVES		waveform and vector exchange program


Now you may jump to:


Home - NASA Office of Logic Design
Last Revised: February 03, 2010
Digital Engineering Institute
Web Grunt: Richard Katz
NACA Seal