ASIC Guide Glossary

NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

The NASA ASIC Guide: Assuring ASICs for SPACE


AC parameter
A time quantity, usually expressed in nanoseconds, used to describe a transient characteristic of a microcircuit, such as access time and propagation delay.

access time
The maximum time interval between stimulus and response required to execute a particular function such as a memory cell call. Access time may correspond to a device as a whole or to a subfunction of a device.

addressable storage elements
Registers that can be accessed directly, either as part of a parallel bus or through a serial shift register chain. Addressablility for storage elements is sometimes a desired operational mode and other times needed for testability.

application specific integrated circuit (ASIC)
An integrated circuit that is designed according to the needs of a particular system. Since most space systems are produced in low volume, their ASICs are also necessarily fabricated in low volume.

at-speed test
A test that applies test vectors to a device at the device's actual operating frequency.

attitude and articulation control system (AACS)
The electronics of a robotic spacecraft that maintain or change its orientation through a combination of position sensing and yaw/pitch/roll control (attitude), and maintain or change the physical relationship of one part of the spacecraft to another (articulation).

automatic test pattern generation (ATPG)
The creation of signals by computer-run algorithm for use with an integrated circuit tester. ATPG signal sets (often called test vector sets) are commonly developed in conjunction with a specific design- for-test technique, such as scan design.

boundary-scan design
A design-for-test approach for ICs whereby all device input and output pads are designed in test mode connect together as a serial shift register, allowing test data to be read in and read out of a circuit while the circuit is in its target system. A popular boundary- scan standard is IEEE 1149.1.

bridged interconnect
A short between two metal lines caused by imperfect manufacturing controls.

Built-In Logic Block Observation (BILBO)
A technique used for self-test whereby a linear-feedback shift register generates a sequence of test vectors that propagate through a combinational circuit to a register. The register compares the resulting value or values against a stored signature to confirm that the circuit is defect-free. BILBO may be used in conjunction with some type of scan logic to allow most parts of a complex IC to be self- tested.

A test defined in MIL-STD-883 that involves applying high-voltage electrical tests at high temperatures for long periods to detect and discard parts that would fail before their specified lifespan.

A transistor-level version of an ASIC function. Cells are usually the simplest level at which gate array and standard cell ASIC designers design.

cell library
A collection of information about ASIC cells, usually created, tested, and verified by the ASIC manufacturer for a specific fabrication process. Cell libraries given to ASIC designers include function and performance information required for circuit design on a CAD system.

The first of two steps (certification and qualification) involved in becoming a supplier of QPL or QML microcircuits. Certification is awarded after a vendor has shown that all government-specified methodologies are set up correctly.

A set of tests applied to a fabrication process, a microcircuit, or a subsystem used to measure critical process or performance parameters under all anticipated electrical and environmental conditions, and to measure how changes in those conditions and parameters correlate.

circuit node
The net or interconnect between a circuit element output and all electrically connected inputs it feeds.

circuit port
An input or output "pin" of a circuit element. For example, a two-input NAND gate would have three ports--two inputs and one output.

class B
One of two quality levels (class B and class S) for QPL microcircuits. NASA considers class B microcircuits qualified for ground-based systems, and some for high-reliability space systems.

class Q
One of two quality levels (class Q and class V) for QML microcircuits. NASA considers class Q microcircuits qualified for ground-based systems, and some for high-reliability space systems.

class S
One of two quality levels (class B and class S) for QPL microcircuits. NASA considers class S microcircuits qualified for space systems; the only major general exception is the microcircuit's demonstrated ability to operate in its anticipated space radiation environment.

class V
One of two quality levels (class Q and class V) for QML microcircuits. NASA considers class V microcircuits qualified for space systems; the only major general exception is the microcircuit's demonstrated ability to operate in its anticipated space radiation environment.

complementary metal-oxide semiconductor (CMOS)
CMOS is a logic design style using combinations of PMOS and NMOS transistors, such that only one transistor of each pair can switch states at a time. Under DC or low frequency conditions, this logic design style allows steady state current to dissipate only through leakage. Relatively large power is dissipated only during transistor switching at mid- to high-frequencies when there are brief periods where both types of devices are on simultaneously.

Synonomous with "part." See part.

computer-aided design (CAD)
Any of a number of computer-based tools which assist a designer. CAD tools are vital for a number of phases in designing integrated circuits because they greatly facilitate entering, verifying, tracking, and storing massive amounts of complex information required.

Metal line connections to transistors, to output pins, and to each other between interconnect layers.

core logic
The portion of a circuit that implements the circuit's primary functions. Interface logic (I/O pads) and test logic are not usually considered part of core logic.

critical path
An interconnect line in a microcircuit design with signals requiring strict timing behavior relative to other interconnects in order for the device to function properly. Identifying critical paths is important to preserve correct timing relationships as the ASIC design progresses from logic level, through layout, to final working part.

current fault
A fault revealing a defect that causes an unwanted path between power and ground. A test method called IDDQ testing detects the anomalously large currents produced by these defects.

DC parameter
A voltage or current quantity, usually expressed in volts or milliamps, used to describe an I/O characteristic such as input voltage.

A physical flaw in a microcircuit that may inhibit microcircuit performance or that may cause a chain of events that will inhibit performance in the near future. Defects include gate oxide shorts, interconnect imperfections, leaky reverse-bias pn junctions, etc.

delay fault
A fault revealing a manufacturing defect or design flaw that causes a signal to be delayed outside of its specified delay.

delta measurement
A measure of a parameter change, such as the operating voltage, taken before and after test stress, such as radiation exposure or burn-in.

Defense Electronics Supply Center (DESC)
An organization formed by the Department of Defense to ensure the supply of known-quality electronic parts to government programs.

design verification
A variety of computer simulation procedures used to determine whether a design conforms to its specification. These tools verify the function, performance, testability, radiation hardness, and other specified aspects of a design.

design for test (DFT)
1) The set of design techniques used to make a circuit testable. 2) A designer's disposition to consider testing as well as performance when choosing design strategies. Examples of DFT strategies include scan design, built-in self test, and avoidance of redundancy.

detailed specification
A specification unique to each device, quantifying all important parameters regarding function, performance, physical dimensions, test parameters, etc.

Synonomous with "part." See also part.

The method used to mount an integrated circuit to a substrate, most often the device's package. Methods include gold-silicon eutectic bonding, various solders, and conductive (and nonconductive) epoxies.

die-shear test
A test to determine the strength of the bond between a die and its package.

The United States Government Department of Defense

electronic design interchange format (EDIF)
A standard form of describing a circuit/device netlist

The mass transport of metal ions in aluminum metal lines, potentially thinning and thus inhibiting conduction paths. This occurs when ions are pulled from their lattice sites through electron collisions and thermal exitation.

electrostatic discharge sensitivity (ESD)
The level of susceptibility of a device to damage by static electricity. ESDS classification testing finds the susceptibility levels and provides the basis for assigning ESDS class.

end-of-life effects
Failure mechanisms that cause a steadily increasing rate in degradation of a device's performance parameters, occurring relatively late in the device's specified lifetime. These include time- dependent dielectric breakdown, electromigration, hot carriers, metal stress voiding, and ionizing radiation.

end-of-line tests
Tests, also called screens, that a microelectronics vendor uses immediately after manufacturing the parts, to detect and reject parts with defects. Many vendors use end-of-line tests defined in MIL- STD-883, Method 5004.

engineering parts
Parts fabricated for characterization purposes that are similar in form, fit and function to flight parts.

fabrication (process)
A manufacturing line capable of creating one or more device types. A vendor may have several fabrication processes.

failure analysis (F/A)
1) A formalized approach to determine the cause and nature of part failures and to recommend corrective actions. 2) The organization that performs such work.

failure mechanism
The underlying cause of a defect. For example, a detected circuit open (a "fault") may be caused by a break in an aluminum interconnect (a "defect"), which in turn was produced by electromigration activity (the "failure mechanism").

The manifestation of a device defect, detectable externally. Faults are detected by comparing specified device parameters and behavior with actual measured parameters and behavior.

fault coverage
The ratio of the count of all detectable faults in a circuit to the count of those faults detected by a particular test set (set of test vectors). The ratio is usually expressed as a percentage and is most often associated with stuck-at fault modeling and testing.

first pass silicon
A device that works, according to its specification, the first time it is manufactured.

flight part
A fabricated device intended for use in the final (flight) system. This device has undergone a set of tests and screens described in its specification that make it eligible for flight application.

functional test
A test designed to demonstrate the ability of a device to correctly perform one or more intended functions over some range of input conditions and internal states.

Gallium Arsenide (GaAs)
A microelectronics process technology used for high-speed applications. Gallium arsenide semiconductors can switch faster than silicon-based semiconductors because the material has approximately six times greater electron mobility than silicon.

The semiconductor region in a MOS transistor, located between its source and drain regions and having the opposite doping polarity to them. The gate forms a conducting path from source to drain when exposed to an electrical field of sufficient magnitude.

gate count
(1) The total number of cells in a circuit. (2) The total two-input gate "equivalents" in a circuit. Gate equivalents are used where the cell count is misleading because a single count for complex single cells makes an ASIC appear simpler, smaller or more easily routable than is actually the case.

gate delay
The time required for a signal to pass through a single gate. It is often specified as the time between which a gate input achieves a specified voltage and its output(s) achieve a specified voltage driving a specified load. Gate delays are futher described under various conditions, including worst-case process, post-radiation, and high and low temperature.

gate oxide
The thin layer of dielectric between n- and p-type materials in a CMOS transistor. In many CMOS processes capable of building 1 micron channel-length transistors, this oxide thickness is on the order of one hundred angstroms.

general specification
A contractual document signed between a customer and an ASIC vendor that provides a framework for a series of ASICs to be built for that customer on one of the ASIC vendor's fabrication lines. It is augmented by a number of other contractual elements including a statement of work and detailed specifications for each individual ASIC design.

A passivation approach using a pyrolytic glass-deposition technique, providing a protective glass cover for a semiconductor device.

hard macro cells
Hard macro cells implement functions using an optimized layout design, usually to achieve maximum performance and transistor densities.

Hardware Description Language (HDL)
A CAD tool used for description and simulation of system and part microelectronics hardware at three major levels of abstraction: behavioral or algorithmic, register transfer level (RTL), and gate. ASIC HDL models at the RTL level are frequently automatically compiled into ASIC vendor's cell libraries to avoid manual gate-level design time and improve accuracy relative to high-level system modeling.

The ability of a device to continue to meet a challenging specification over extended periods of time.

hot carrier
A charge-carrying particle with sufficient energy to pass over a diode barrier. In CMOS transistors, these particles are electrons ("hot electrons") that cross over the semiconductor-metal junction. Repeated occurrences of this phenomenon can lead to device failure.

hot chuck
A fixture holding IC die or packages that can be heated for an assembly operation or for temperature testing.

A microcircuit consisting of two or more physically separate electronic components (ICs, discrete transistors, resistors, capacitors, inductors, etc), mounted on a single interconnecting substrate and packaged in a similar fashion to individual integrated circuits. Recently, hybrids made mostly from ICs and built on silicon, ceramic, and fiberglass substrates have been called multichip modules or MCMs.

A very powerful test for determining manufacturing-induced defects involving measurement of quiescent power supply current. Many defects change the amount of quiescent current drawn by a device, therefore a change in quiescent current is a very sensitive detector of defects that would otherwise be invisible until a functional failure occurs.

IEEE 1149.1
A standard for a test circuitry bus, developed by the Institute of Electrical and Electronic Engineers (IEEE). It defines a serial bus with control lines and control circuitry which allow ASICs and other VLSI devices to be tested in their system boards (if the boards are also designed to the standard).

infant mortality
The observed tendency for some electronic devices to fail in the first few months of operation. In-line and end-of-line tests are used to detect defects that cause infant mortality.

in-line tests
Tests applied to semiconductor wafers during the fabrication process to detect defects. Defects detected in-line can save an IC vendor from spending additional resources on further fabrication of devices which would ultimately fail end-of-line testing or screening.

Input and Output.

integrated circuit
See microcircuit.

A parasitic effect on CMOS devices where sufficient current is injected into a substrate to cause the occurance of a pnpn or npnp silicon-controlled rectifier (SCR)-type structure. When this structure forms a low-impedance path from power to ground, the resulting high current flow can stop a device from functioning and may permanently damage or destroy it. Latchup may be induced through a number of ways including unusually high supply voltages and currents induced by passing high-energy charged particles (galactic cosmic rays, etc.) through a circuit substrate.

latent defect
A microcircuit defect that is not likely to inhibit performance until well into the microcircuit's lifetime.

leakage current
All undesirable stray current in a microcircuit.

level-sensitive scan design (LSSD)
A design-for-test technique using a well-defined methodology that includes two test clocks and modified bit-storage structures to achieve high-levels of testability.

See cell library.

life test
An end-of-line test defined in MIL-STD-883 that entails stressing a microcirucit at high voltage and temperature for 1000 hours to accelerate failure mechanisms responsible for infant mortality. A common variation on a 1000 hour life test is a 2000 hour life test done on half the number of devices. This better accommodates most ASIC orders, which are often small volume buys with relatively high per piece prices.

linear energy transfer (LET)
The amount of energy transfered to an IC's active area by a traversing charged particle.

logic gate
Physically, a logic gate is a transistor circuit which allows voltages to pass through based on simple logic rules applied to its inputs. These structures include logic functions such as NAND, NOR, AND, OR, XOR, XNOR, NOT, etc. In CAD simulation, a logic gate may be represented by its Boolean equivalent or by more complex representations which include delay and other parametric information.

The quantity of microelectronic devices built at the same time. It is typical for an ASIC lot to consist of all parts built from a certain set of wafers. Typical wafer sets range in size from five wafers to twenty five wafers and are physically moved through the vendor's fabrication facility at the same time.

A thin photographic film used to transfer part of a circuit pattern to the surface of a semiconductor wafer. A number of masks are used in combination with various additive and subtractive operations, to create the integrated circuits on a wafer.

metal stress voiding
The undesirable creation of voids (holes) in IC metal lines by thermal, chemical, or mechanical phenomena.

(1) One or more layers of microcircuit metal conduction paths fabricated over the transistor layers and separated by a dielectric, often SiO2. (2) The fabrication steps that produce these metal layers.

A circuit consisting of a number of transistors built and interconnected on a single semiconductor substrate. The smallest present-day microcircuit transistors have an approximate gate- length of 0.5 micron.

A version of an electronic circuit on a CAD system consisting of all of the circuit element names/reference designators, listed with their input and output signal names, in a format similar to <element name><input signals><output signals>. Netlists are the primary form of a circuit used for CAD simulation. Schematic versions of circuits almost always have to be compiled into netlists before simulation or manufacture is possible.

non-recurring engineering (NRE)
Engineering activity performed by an ASIC vendor's engineers to bring an ASIC design to manufacture. This activity can include initial logic design support, chip layout, mask generation, test generation and other services. The costs associated with NRE are contrasted with the piece price of ASIC parts which are "recurring" costs, based on part quantity.

oxide layer
A layer of an integrated circuit created to provide isolation between conductive layers. See also gate oxide.

parametric test
A test that measures and compares an ASIC part's voltages, currents, and timing against specified values.

parasitic transistor leakage
A transistor defect where inadvertent channel inversion causes leakage from drain to source.

An active or passive device used in an electronic system. Less frequently, a "part" may refer to other members of an electronic system such as a printed circuit board. Synonomous with "component" and "device."

part acceptance
The set of methodologies used to show that a fabricated device is likely to perform according to its specification.

The technique of providing a protective, isolating coating on the top of a semiconductor device. Usually silicon dioxide is grown to provide this coating, but other materials are also used, such as glass. See glassivation.

path delay
The time required for a signal to traverse through a wire between two circuit components.

percent defective allowable (PDA)
The maximum observed percent defective that will permit a lot of ASIC parts to be accepted after the specified 100 percent test (from QML).

process maturity
A point at which a process requires minimum changes to achieve acceptable yields. For a certain ASIC, a mature process is one that has successfully produced many devices of similar or higher complexity and has successfully built all of the cells to be used. Caveat: a process that is old may not have desired qualities— equipment breakdown, loss of crucial personnel, low demand, and low volume of an older process may make it problematic to maintain yield and, therefore, reliability.

process monitor (PM)
A structure built into a chip or wafer used for the regularly scheduled periodic sample measuring of a parameter during normal performance of production operations in accordance with the manufacturer's approved program plan. The parameter to be measured, the frequency of measurement, the number of sample measurements, the conditions of measurement, and the analysis of measurement data will vary as a function of the requirements, capability, and criticality of the operation being measured.

process stability
The degree to which a process undergoes change to achieve acceptable yield. See process maturity.

proof-of-design part
A fabricated ASIC used to verify ASIC functionality before fabricating engineering and flight parts.

A fabricated ASIC used to verify any or all of the following for the ASIC and/or its system: function, performance, operating limits, and reliability. Proof-of-design parts and engineering parts are prototypes.

A transistor condition where the drain-substrate depletion reaches the source and causes leakage from the drain to the source.

Qualified Parts List (QPL)
A government standard listing of electronic parts. Also, a program for the qualification of devices for inclusion in the list. MIL-M-38510 describes this program.

A three-step process of 1) making a specification public; 2) creating an entity that implements the specification; and 3) demonstrating that the implementation matches the specification. In conjunction with certification, qualification activity is used to establish a vendor's adherence to the QML or QPL program requirements.

The ability of a device to meet or exceed the expectations of its specification beyond some minimum period time.

quality assurance (QA)
The group responsible for verifying that a microelectronics vendor delivers as promised. They are involved in approving a vendor's facilities early in a procurement cycle and then comparing the actual delivered devices with the device contract.

Quality Management Plan (QM Plan)
The plan for control of management, engineering and production processes that a microelectronics vendor develops to show that their facility and personnel meet all requirements of the QML program as described in MIL-I-38535.

Qualified Manufacturer List (QML)
A list showing microelectronics vendors qualified to MIL-I-38535.

Qualified Products List (QPL)
A list showing electronic devices qualified to MIL-M-38510. At present, there are plans to combine the QML and QPL.

quiescent current
The normally low current (measured in milliamps or microamps) that flows from power to ground in a CMOS integrated circuit.

radiation hardness
The ability of an integrated circuit to retain function and performance after being exposed to a specified amount of radiation. A circuit that does retain specified function and performance is often called rad hard.

radiation hardness assurance (RHA)
The portion of product assurance which insures that parts continue to perform as specified or degrade in a specified manner when subjected to the specified radiation environmental stress.

The characteristic of a device that relates its expected level of performance to the environmental and operating conditions to which it is subjected, as a function of time.

register transfer level (RTL)
A circuit modeling level based on the flow of data from register to register.

scan path
One or more serial shift register chains through which test signals are applied and test results are observed. The scan path registers may also be used in the normal (non-test) mode of the circuit for status registers, data storage, etc.

schematic capture
The act of entering a circuit schematic into a graphical CAD tool.

SHMOO plots
A two-dimensional plot of data, usually used to isolate failure parameters.

silicon-on-insulator (SOI)
Microelectronics process technologies used for radiation-hardened applications. Two types of SOI technology are Silicon on Sapphire (SOS) and Separation by IMplanted OXygen (SIMOX).

silicon-on-sapphire (SOS)
See silicon-on-insulator.

A computer-based system used for designing and testing one or more aspects of ASIC models.

single-event burnout (SEB)
A type of single-event effect (SEE) that causes a permanent low resistance path between the gate and the substrate of a transistor.

single-event effects (SEE)
Undesirable effects on an integrated circuit caused by energy transfered to its active area by the passage of a charged particle through it.

single-event latchup (SEL)
A type of single-event effect. See latchup.

single-event upset (SEU)
A type of single-event effect (SEE) that causes a temporary change in the logical state of a transistor input or output node. SEUs are most hazardous when they change the state of a structure, such as a register or a memory cell, causing an incorrect value to be stored.

soft macro cells
Soft macro cells are complex functions in a vendor's cell library built up out of hard-wired primitive cells.

standard cell
ASIC design cells that are optimized by transistor sizing for speed and die area. This transistor sizing requires standard cell ASICs to be unique for all process levels. In contrasts gate array cells are built from identically-sized transistors but require customization only at the interconnect levels.

standard evaluation circuit (SEC)
A device used for maintaining qualification of a QML fabrication line, it is typically a memory device.

standby current
The current drawn by an idle device while in normal operating mode. See quiescent current.

statistical process control (SPC)
A technique for keeping a process within specified performance limits by measurement, statistical analysis, and feedback. SPC is often used along with Design Of Experiments (DOE) to improve yield and provide other enhancements to a microelectronics fabrication line.

step coverage
The quality of metal interconnect in an integrated circuit where it steps vertically from one layer to another. Usually described as a percentage of the flat metal interconnect's cross-section, i. e. a step coverage 10% of normal.

stuck-at fault
A deduction about a circuit problem based on a comparison of expected logical outputs to actual outputs. The underlying assumption is that a gate input or output is inhibited by a defect from switching states and is "stuck at" a particular value.

The structure of an IC refers to the actual combination of logic elements, transistors, or other physical devices. For example, a functional description of an IC may be implemented by many different logic-level structures and a logic-level schematic may be implemented by many different transistor structures, etc.

structural test
A test to determine if the structure of a device is correct as specified. Structural tests may be done on many different levels of a design or part. Common structural tests include stuck-at fault tests and IDDQ tests.

Technology Characterization Vehicle (TCV)
A device used for the qualification of a QML manufacturing line.

Technology Review Board (TRB)
A government-approved committee, consisting of a QML manufacturer's employees, that internally develops, maintains, and continuously improves the manufacturer's QML Quality Management Plan as defined in MIL-I-38535. QML requires this group to implement change control and to communicate with DESC and customers about change.

temperature cycling
A test defined in MIL-STD-883 that involves exposing parts to alternate extremes of high and low temperature. This is done to detect and discard parts that would otherwise fail from temperature changes experienced during their target applications.

test access port (TAP)
A set of pins, defined in IEEE 1149.1, used to implement boundary scan and other scan test interfaces into a circuit. See also boundary scan design.

test vectors
A set of circuit stimuli (expressed either as logical 1s and 0s or voltage levels) and expected circuit responses (expressed as logical 1s and 0s, voltage levels, impedence levels, unknowns or don't cares) that are used to first test a circuit simulation and ultimately fabricated devices.

time-dependent dielectric breakdown (TDDB)
The gradual and undesirable degradation of the gate oxide layer in MOS transistors from thermal and mechanical phenomena.

toggle coverage
The ratio of the number of nodes toggled by a set of test vectors to the total nodes in a circuit.

total ionizing dose (TID)
The accumulated amount of ionizing radiation a microelectronics device receives.

top-down design methodology
A method of controlling the complexity of design development. Top down design begins with the most abstract description of a system, and breaks this into subdescriptions. The lowest level should describe those devices purchased outside of the organization.

Total Quality Management (TQM)
An organizational management approach noted for making all individuals responsible for improving the quality of goods and services supplied. Activities in TQM include a rigorous program of on-going internal organizational analysis, benchmarking against competitors, explicit change control and meaningful progress measurement in all areas. TQM techniques are called out in the QML program.

A quantum-mechanical effect causing particles to pass through an energy barrier without having the energy normally associated with that barrier. In the context of transistors, electron tunneling has been observed across opens in metal lines, causing logic gates to function at low frequencies but fail at high frequencies.

very high speed integrated circuit (VHSIC)
A series of government programs designed to stimulate development and standardize complex microcircuit technology.

VHSIC Hardware Description Language (VHDL)
A government-specified HDL. See Hardware Description Language.

voltage fault
A defect present in a device that makes itself known as an incorrect voltage level.

A disk of semiconductor material that forms the base on which a number of identical integrated circuits are built. In some cases, two or more designs may be built on the same wafer. In most facilities, five or more wafers are brought through each fabrication step simultaneously in a group known as a wafer lot.

wafer acceptance
A set of tests performed on integrated circuit wafers designed to distinguish between wafers that will yield a high percentage of good dice and those that will not.

wafer lot
See lot.

wafer probe
A facility that connects the die pads on a wafer to a tester and allows one or more individual die to be tested. Wafer probing is often used as part of wafer acceptance.

A version or versions of a circuit whereby certain key distributed parameters, such as temperature, process variation, and radiation effects, are set to values within their specified ranges that cause the circuit to have maximum deviation from its nominal operation.

The percentage of successfully-fabricated dice in a given wafer lot.

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