NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


The NASA ASIC Guide: Assuring ASICs for SPACE

Appendix Two: Government Qualification Programs

Objective:

To discuss the listing of parts or vendors that conform to a carefully developed set of standards.

Since the microcircuit device industry began more than 30 years ago, the Department of Defense (DoD) has developed several standards for the industry. Today, the standards that apply to ASICs are MIL-M-38510 and MIL-I-38535. Governmental institutions use these standards to assure that the microcircuits they receive from manufacturers conform to predictable quality levels.

Specifications MIL-M-38510 and MIL-I-38535 outline all the procedures necessary for parts and vendors to be included on government-endorsed lists. MIL-M-38510 refers to the "Qualified Products List" (QPL) and MIL-I-38535 refers to the "Qualified Manufacturers List" (QML). QML differs from the more established QPL in that under QML the government qualifies a manufacturer's entire fabrication process rather than qualifying the device types fabricated by that process. MIL-M-38510/605-608, the QPL gate array program, also takes this newer approach, since each gate array design is unique and cannot be qualified separately.

Qualified Products List (QPL)

Military standards for integrated circuit qualification grew as an extension of discrete device qualification. In the days when discrete devices were new, high defect rates and unreliable electrical performance were of immediate concern to the DoD. The first standards of long-standing use that addressed this concern were MIL-STD-750 and MIL-S-19500, which set screening standards for discrete devices that are still in use. But when integrated circuits entered the scene, it rapidly became evident that they required new screening standards.

These new standards were compiled in MIL-STD-883, and have been periodically updated since. Along with MIL-STD-883, the Defense Electronics Supply Center (DESC) developed a methodology to create an ongoing list of microcircuits (QPL) that qualify for use in military and space applications. The methodology aims to develop well-documented and unchanging specifications for certain parts so that amidst a tendency for unreliable microcircuit production, governmental standards could reside over a small and rigidly defined subset of microcircuit products. MIL-M-38510 (QPL) contains both the methodology and the continually updated list of qualified parts. The QPL system has successfully qualified integrated circuits for over 20 years.

THE QPL APPROACH TO QUALIFICATION

The methodology for annotating a part to the QPL consists of four steps: First, the governmental party with primary interest in the part writes a specification called a "slash sheet." Second, the vendor fabricates the part on the process line intended to be uniquely qualified to supply the part. Third the vendor tests the part extensively to verify that it conforms to its specification. Finally, DESC specifies end-of-the-line testing required each time the vendor fabricates the part to screen for anomalous defects. Depending on the application of the part, the manufacturer may apply these end-of-line tests on every part or on a sample of parts from each lot. MIL-STD-883 contains most of these tests.

QPL annotation consists of two stages for each device: certification and qualification. For certification, the government's qualifying agency must approve the manufacturer's quality assurance program. Certification requires extremely thorough documentation to assure that each part will be fabricated identically. For qualification, DESC must verify that each part truly conforms to its slash sheet.

QPL manufacturers must follow the methodology outlined in MIL-M- 38510 and the certification requirements for Joint- Army-Navy (JAN) microcircuits outlined in MIL-STD-976. These specifications address several areas related to design specification, fabrication (such as statistical process control and parametric monitors), change control, testing, and record maintenance.

After DESC grants certification, the manufacturer fabricates parts according to their slash sheets and performs government-approved testing on those parts. These tests generate substantial reliability data for the Qualification Test Report to be submitted to DESC. Upon approval, DESC qualifies the part and annotates it to the QPL.

The government grants two levels of certification: Class B and Class S. Class B parts target tactical military systems and low criticality space systems, and Class S parts target strategic military systems and high criticality space systems. Class B parts must qualify within one year of certification and Class S parts must qualify within two years of certification.

Qualified Manufacturers List (QML)

Since the late 1960s two major developments have occurred in the semiconductor industry that have brought about a new system of qualification focusing on the process level, rather than on the device level.

The first and most significant development is increased device complexity. VLSI (very large scale integration), ULSI (ultra LSI), WSI (wafer-SI), and SySI (system-SI) reflect this complexity. As parts become more complex, developing thorough QPL documentation on each part becomes more and more labor intensive. Now that parts can employ over a million transistors, it is impossible to specify the design, fabrication and test parameters to the same level of precision as was possible when QPL originated and parts had only a handful of transistors. The original goal of QPL, to fully define and qualify every aspect of each part type, is becoming less and less practical. This is particularly true for ASICs, since each design is different. Thus when DESC added ASICs to the QPL (gate arrays defined by slash sheet 608) QPL, set a precedent for leaving many details of part design and fabrication unspecified.

The second development is simply the nationwide improvements in semiconductor fabrication processes. Improved manufacturing techniques and programs such as statistical process control (SPC) and Total Quality Management (TQM) have created more reliable fabrication lines challenging the need to separately qualify each product that comes off a fabrication line. Thus, QML and the QPL gate array specification focus their attention on qualifying a process, rather than on each part fabricated by those processes.

THE QML APPROACH TO QUALIFICATION

QML requirements, like QPL, are broken into certification and qualification requirements. But instead of qualifying individual parts, the QML program qualifies a process line in general. Individual parts still need specifications called "Standardized Military Drawings" (SMD), but they are under much less governmental control than QPL's "slash sheets."

Unlike QPL, the manufacturer controls the fabrication process rather than the government. To become a QML supplier, a manufacturer organizes an in-house team of personnel who represent all critical areas of microcircuit production. This team, called the Technology Review Board (TRB), develops a Quality Management Plan (QMP), which the government approves.

The TRB maintains certified and qualified processes, process change control, reliability data analysis, failure analysis, corrective actions, QML microcircuit recall procedures, and qualification status of the technology. The board has representatives for all stages of the fabrication process, from design through testing. Board members oversee and approve the QMP with many self-imposed programs developed in accordance with the QML specification, MIL-I-38535. Programs may include a quality enhancement plan, an SPC plan, a change control program, etc. Once validated by a government-organized QML review board, all programs are subject to revalidation reviews not to exceed a two- year frequency, including any number of drop-in reviews.

QML certification resembles a QPL audit, but covers many more areas than a QPL audit. Programs in MIL-I- 38535 that DESC verifies include QMP documentation, process interface procedures, design verifications, and wafer fabrication programs. Mandatory wafer fabrication programs include SPC and in-process monitoring, a technology characterization vehicle (TCV), a standard evaluation circuit (SEC), a parametric monitor (PM), and an electrostatic discharge sensitivity (ESD) plan. All of these programs already existed and were operating at some foundries, but they are now monitored requirements of QML.

To qualify under QML, a vendor must successfully build and screen at least two complex microcircuit designs for a certain time and in a sufficient quantity. Qualification verifies that their certified process can produce acceptable devices given the usual variations in process and materials.

STEPS TOWARD PRODUCING A QML-QUALIFIED ASIC

The user and the vendor must communicate effectively since they constantly depend upon each other. Under QML, users who are designing QML ASICs must conform to the vendor's qualified methodology. This means a designer must choose a QML vendor and get acquainted with that vendor's design rules before designing the ASIC. Once the ASIC is designed, the vendor verifies the design according to QML standards and fabricates the ASIC. At this point, the designer verifies the ASIC to make sure it performs as designed. If all aspects of the vendor's QML plan have been satisfied, the ASIC gets stamped "QML."

The QML system allows for parties, other than the user and the vendor, to fabricate and qualify QML parts. These third parties, along with the primary vendor, must be qualified by DESC. The third parties may do any or all of the work required to produce QML devices, including design, fabrication, assembly, and testing. Recently, QML has allowed non-qualified third parties to do ASIC design work, as long as they conform to the QML vendor's qualified methodology.

LIMITATIONS OF QML

Three factors limit widespread acceptance of QML: It is new, only seven years old; it is unproven; and few manufacturers are QML qualified. Of those manufacturers certified as of 1993, DESC has qualified only two for space applications (Class V with Radiation Hardness Assurance). Although QML's methodologies should prove to produce parts equal to those produced using QPL's methodologies, no-one has yet undertaken reliability studies of QML parts. Thus it will take several more years before the integrated circuit industry accepts QML as the definitive system for complex semiconductor fabrication.

A Brief Comparison of QML and QPL

Although the details of QPL and QML strategies differ, actually implementing the two programs usually turns out to be more similar than different. Both QML and QPL recognize process-level qualification as particularly important for ASICs, since each design is unique, making predefined part-level specifications incomplete. We suspect that the two systems will eventually merge. For the time being, this guide considers QPL and QML equally capable of producing space-quality ASICs

The fundamental difference between QML and QPL lies in implementing the requirements. QPL specifies how the vendor implements the requirements, whereas QML allows the vendor to determine their own way of satisfying the requirements. In other words, QPL procedures are government specified and change- controlled; QML procedures are manufacturer controlled.

The Future

Since the beginning of the QML program those in the integrated circuit industry have speculated about the eventual combination of the QML and QPL programs. Events during the last quarter of calendar year 1992 have accelerated this merger. At the time of this writing, we expect to see a combined program by the middle of 1993.

We also anticipate that the new QML will have an increased role in off-shore microelectronics work. This could include off-shore design, fabrication, test and assembly.


Now you may jump to:


Home - NASA Office of Logic Design
Last Revised: February 03, 2010
Digital Engineering Institute
Web Grunt: Richard Katz
NACA Seal