NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

The NASA ASIC Guide: Assuring ASICs for SPACE

Chapter Five: Computer-Aided Design (CAD) Tool Analysis


To provide the evaluating team with a guideline to ensure that the tool set meets the project requirements and represents the most efficient option for the design team and the vendor.

The evaluating team determines whether the vendor's tool set has adequate capability for producing the ASIC to the customer's requirements. For a successful ASIC project, the evaluating team must understand the design team's needs as well as the many considerations and trade-offs involved in the complex process of evaluating a vendor's tool set.

Modern ASIC projects require a complete set of computer-aided design (CAD) tools that map closely to a vendor's entire ASIC flow. Incompleteness, lack of proper integration, divergence from a vendor's flow or other inadequacies seriously endanger the success of an ASIC program.

ASIC vendors support a set of CAD tools that allow their customers to perform ASIC logic design and design verification with the vendor cell libraries. These tools must offer flexibility to support different choices of customer design approaches. They must also offer ways to manage the massive amounts of data generated in the design processes.

Vendors often have additional CAD tools in-house to perform tasks such as physical layout or tester program generation that designers rarely use. The evaluation of a vendor's supported tool set must show that it can deliver all necessary design and design verification functions completely and in a timely fashion, and that the vendor has adequate training programs and technical support available.

Figure 2.5.1 ASIC Design Tool Flow

ASIC engineers and managers depend heavily upon tools throughout the ASIC development cycle (see Figure 2.5.1). The following list shows personnel who typically use ASIC tools and the tasks for which the tools are used:

To meet the tight design schedule of an ASIC development program the team should make sure the vendor's tools suit the needs of all the responsible parties.

In evaluating the tools make sure of the following:

When evaluating tools, the team also needs to consider a second source for foundry or design work, testability requirements, and future ASIC designs. Your ASIC or system designers will probably have some preferences for certain CAE tools (Mentor, Cadence, etc.). These preferences must be considered if they translate into strong, economic and programmatic justifications.

This chapter examines ASIC development tools, test equipment, industry standards for CAD tools, and why it behooves us to follow these standards. The discussion extends to design management tools that help in making design decisions. It also examines the support needed from a vendor for tool training, documentation, and solving tool technical issues.

ASIC Development Tools Analysis

Tool analysis plays an important role in vendor evaluation. Designers design and verify ASICs with CAD tools. The evaluating team should make every effort to identify vendors whose CAD tools best suit the needs of the designers. An evaluation of the vendor- supported CAD tool set must demonstrate capabilities for:

This chapter will consider the main features and options of the above mentioned CAD tool set available to the design team.


System or chip designers use design partitioning tools to ensure that the proposed design will fit in the die package provided by the vendor. If the design cannot fit in one package because of pad pin limitations or die size limitation, then the design is partitioned so that it will fit in more than one package. The team should make sure the vendor offers design partitioning tools.


These tools capture a design and prepare it for simulation. The means of capture vary. The design requirements dictate whether the design tools must have all or some of the following options:

We recommend that design capture tools also have the following features:


For designs that use Boolean equations, HDL or state diagrams for design capture, the designer may convert to gate level description using the synthesis process. Then, the designer maps the gate-level description to the target design library and optimizes for speed, area, or power consumption.

Alternately, a designer may enter a design directly into a CAD system at the gate or cell level. This has been the most common method of ASIC design since the early 1980s.

We would like to promote the use of a HDL to describe a design. Behavioral models allow an engineer to perform a board level simulation to verify the functionality and interface of a design. The software model can then be converted to gate-level design using synthesis and optimization tools. These tools should have the following features:


"Modern ASIC projects require a complete set of CAD tools that map closely to a vendor's entire ASIC flow."

Test tools should support test generation using faults that closely model real defect behavior.

Whatever fault model is used, the tools should support the designer's need to follow DFT guidelines in achieving the required fault coverage. CAD tools often automate the more common test methodologies, such as full scan design.

Test Synthesis Tools
If DFT requirements dictate using scan cells, the vendor test synthesis tool should support automatic insertion of scan cells. The tool should support partial scan and/or full scan design, depending upon the vendor's DFT methodology.

The evaluating team must explore test synthesis in conjunction with the ATPG tools available.

Automatic Test Pattern Generation (ATPG) Tools
ATPG tools typically generate test vectors to achieve high percentage stuck-at fault coverage. Usually these programs expect a scan-based synchronous design to allow the generation of high fault coverage test vectors. The ATPG tool should work for partial scan design as well as full scan design, depending upon the vendor's DFT methodology. These tools can also be easily modified to achieve current fault coverage, detecting problems, such as leakage faults in IDDQ testing.


These tools assess whether a design would meet the given requirements under certain conditions normally related to the transistor/gate characteristics. The evaluation team should examine these tools for their support of the following tasks.

Critical Path Tools
The design team uses critical path tools to analyze the critical timing paths in a design. These tools calculate timing information along a path and compare it with a specified timing requirement. They should support both long and short critical path analyses.

Power Tools
The power analyzer determines the power consumption of a design based on a set of test vectors and a careful accounting of transistor switching in the ASIC circuit as it runs these vectors. Under these conditions the power can be calculated if the typical power consumed by a given class of transistor at a given switching speed is known. See Section Three: Chapter 1 for more on calculating circuit power consumption.

The evaluation team should review this tool against actual measured power in a number of sample devices to see if the tool accurately predicts power consumption.


These tools are mandatory to simulate and verify a design for logic and testability functions, timing behavior, accuracy to other representations of the design (behavioral-level, discrete breadboard- level, etc.), and performance in the target system. This analysis verifies that simulations are accurate and that this portion of the CAD tool set provides an effective means for filtering bugs from a design.

The evaluation team should receive evidence of design verification done on ASIC designs similar to the target ASIC design(s). The following discussions of design tools offer additional elements for the evaluation team to use in analyzing a vendor's tool sets.

Logic Simulation Tools
Logic simulation verifies the correct logical operation of a design. The design primitives used at this level must be well characterized. See Chapter 4 of this section.

The logic simulation tool should be able to provide mixed-mode simulation such as a combination of behavioral and structural-level circuit representations. Mixed mode simulations prove very useful for large designs, where a behavioral model represents one or more big blocks and a block receiving detailed analysis is at gate-level representation.

For large designs, 100 percent gate-level simulation can be very slow. Use special hardware simulation accelerators to speed up the simulation process. It helps designers if the vendor-supported logic simulation tool supports at least one of the industry popular hardware accelerators.

Figure 2.5.2 HDL Model Comparison

Fault Simulation Tools
Once the designers create a set of test vectors (logical inputs and output values at the device pins), fault simulation tools calculate the fault coverage through one of two likely methods: probabilistic assessment or deterministic assessment.

Probabilistic assessment of fault coverage uses statistical fault grading. When run on the circuit, the test vector measures only a small fraction of the circuit for fault coverage. Evaluating this sample and obtaining a value gives the "probable" coverage of the vector set for the entire circuit.

Deterministic assessment of fault coverage uses a simulation of the entire circuit. The test vector set measures all parts of a circuit for fault coverage. Though generally considered more accurate than probabilistic assessment, this approach requires a significantly larger amount of computer power, especially for circuits of more than a few hundred gates.

Designers performing deterministic fault simulation often have access to a hardware-based simulation accelerator. This device is similar to the one used for logic simulation of large designs. Often, fault simulation is an option on a logic simulation accelerator.

If using stuck-at fault testing, the evaluation team should verify that the fault grading method supports reporting fault coverage as described in MIL-STD-883, Method 5012.

Simulation Compare Tools
Designers find vendor design tool sets useful for simulating and then comparing simulation results at different stages in a design cycle. Often a designer will create tests for a circuit at a block, or behavioral, level in an HDL. A good tool will then also support tests with a gate-level model of the circuit.

Conversely, tools should support "back-annotation" of an HDL behavioral design to show that vectors developed on a gate- level model can run on a behavioral model of a circuit. This is used for a large multi-chip system design that can only be simulated in its entirety at the behavioral level. Tests developed after a portion of the system has been turned into an ASIC are then run on the system at behavior-level to see if any problems developed while refining the ASIC "block" into a gate-level design.

The evaluating team should thoroughly review simulation compare tools, checking examples.

Switch Level Simulation Tools
This simulation, performed at the logical transistor or "switch level," proves the most accurate "logic" model simulation, because circuits are actually built of transistors and in a digital circuit are "usually" designed to act in the non- linear or "on-off" logical mode. Many switch-level simulators have problems with certain transistors that are not logical structures, such as uni- and bi-directional pass gates. However, the best switch-level simulators have features to deal with these and other common transistor structures used in microelectronic designs.

Evaluators should verify that cell library elements, including hard macrocells and representative soft macrocells, are extensively analyzed and debugged by the vendor with the best switch-level simulators.

Circuit Simulation Tools
Circuit simulation simulates at the transistor level. In contrast to switch level simulation, which uses logical models of transistors, circuit simulation uses parametric transistor models for simulation. Lengths and widths of transistors, along with actual CV data from the target process (usually measured from a test inverter structure), are fed into a polynomial model and used to calculate the behavior of a circuit. SPICE, developed at UC Berkeley, is by far the most common circuit simulator. SPICE also supports modeling with resistors, diodes, capacitors, and inductors.

While the industry considers the transistor level the most accurate, it proves impractical to run on anything but small circuits of several hundred transistors or less. Circuit simulation is most often used to design new gate array and standard cell library cells.


The designer performs timing verification at multiple stages of a design. The designer tries to verify that his design will preserve the ASIC design's functions when encountering circuit delays and other "real-world" circuit timing elements in an actual device. Initial logic simulation usually runs with the simplified timing assumptions of "zero-delay" or "unit- delay."

Then the delays associated with signal propagation times through a logic element are added in and a design is rechecked. Sometimes estimates of delays through element interconnects are included.

Finally, a design is checked with information from the chip layout. In general, this information relates to the actual lengths of device interconnects. This data is "back-annotated" to a design as additional or more precise delay information and the designer reconfirms the proper functionality.

The loading characteristics of the cells combined with the simulation timing mode (spread analysis) determines the worst-case and best- case timing analysis. This analysis allows designers to accurately estimate the maximum circuit speed under different operating conditions.


The vendor engineers usually transform a logic representation of an ASIC into a physical representation that allows the ASIC to be manufactured. The evaluation team should verify the CAD tools that perform this task for accuracy. The tools should also have the capability, known as "back annotation," to pass layout information back to the customer and designer for further verification of the functional and performance effects of layout on the ASIC design.

Transistor Layout / Auto- Router Tools
The transistor layout tool takes a cell-level ASIC representation and, for a given technology, creates a set of layers representing transistors for each cell. These layers are turned into masks used to fabricate the transistors in a part. This tool works in conjunction with a floor plan, which shows approximately where various cells should go on the ASIC die.

The auto-router uses the cell-level ASIC interconnection information and the ASIC cell layout to create layers of interconnections between all cells. Interconnections between transistors within primitive cells and hard macrocells are pre-defined and do not require the use of this tool (they are often routed by hand to obtain the maximum transistor densities). The number of layers created with this tool depends upon the number of layers of interconnect for a given technology. These layers are turned into masks, which deposit films of interconnect metallization and dielectric (insulation).

Layout Verification Tools
This program compares the circuit defined by a schematic diagram with that produced by a layout. The comparison provides information on any differences found. It facilitates both error recognition and layout-to-schematic cross reference.

Features that the evaluation team need to consider include the ability to filter out harmless parasitic transistors and turn on or off filtering of other transistor structures. Check for a clear report format for this tool that allows a designer to quickly zero-in on real problems.

Vendor engineers will most often use this tool, but the team should still be satisfied that it provides adequate checks.

Design Rule Check (DRC) Tools
DRC verifies that a circuit layout conforms to the specification of the process technology design rules. DRCs can range from simple physical spacing checks to complex, conjunctive checks where the result of one rule check provides input for another.

The evaluation team should review the history of the process technology along with evidence of how the DRC rules were developed in conjunction with the maturing process.

Electrical Rule Check (ERC) Tools
ERC verifies the structure and integrity of a network. Designers use this tool to perform basic connectivity checks, device-level parameter verification, and netlist extraction.

Parameter Extraction Tools
This tool generates a representation of an ASIC layout that contains its electrical functionality. This tool can perform device parameter measurement as well as extraction and parasitic device recognition and extraction.

Back Annotation Tools
The back annotation process feeds the extracted device parameter values back into the corresponding schematic design elements. The designer then uses these elements for a final logic simulation as a check on the ASIC layout before masks are constructed and additional fabrication steps begin.


Test generation tools can be part of both the vendor and the customer CAD tool sets. They are used to create tests for both ASIC design and ASIC part verification.

ASIC designers normally create three types of tests:

Structural and parametric tests normally go unchanged to the vendor for part testing. Typically, only a fraction of the functional tests used by the designer will become vendor tests. However, in some cases the vendor may use functional tests as structural tests because, of the three categories listed above, they are the only tests run at full speed. In this case the vendor uses enough functional tests to achieve a certain stuck-at fault coverage or toggle coverage.

The functional test set verifies that a device actually performs the job (correct digital logic) that it was designed to do. Structural tests verify that the device is free of certain manufacturing defects. Parametric tests look at voltages and currents, both statically and dynamically.

In the case of functional and structural tests, the vendor's tester must be able to put a series of logic states on the input pins of the device as well as read the logic states on the output. In the case of parametric tests, the tester must apply voltages and currents, and read every pin for the voltages and currents it produces.

When the team evaluates these tools, they should make sure that the vendor's production tester can test the part at operating speed. Also make certain the following information is available to compare against requirements:

Vendor test generation primarily translates customer test vectors and test parametric values into a test program that will run properly on the vendor's production tester. Verifying that this translation can be done efficiently and accurately is vital for the proper testing of ASIC devices both during and after manufacturing and screening.

Information Management Capabilities Analysis

Standards provide the means for porting designs from one CAD tool to another and from one foundry to another. Find out to what extent the vendor data follows industry standard formats to determine the design approach and second source flexibility.

CAE standards fall into two categories:

Data-interchange standards, such as EDIF, allow movement of data from one system to another making it possible to process the same design on one or more tools.

Tools standards are more sophisticated. The DoD created VHDL, which IEEE established as a standard. VHDL provides the best example of standards for describing electronic components. Many ASIC vendors can take the same VHDL description of a design and perform chip layout and fabrication.

Design Configuration Management Capability Analysis

The ASIC design process produces different versions of design information. ASIC managers must practice complete and consistent information management through every step to the ASIC manufacture. The evaluation team must examine tool sets for the following capabilities.


Configuration control refers to maintaining the proper relationships between tools and design files, from tool to tool, and between design files and design files. ASICs have thousands of data files and perhaps dozens of tools involved. Precise knowledge of which tools have been used on a design is essential. Revisions of tools and data files constantly occur and must be tracked to avoid very expensive incompatibilities.

The industry has only recently introduced automated tools for ASIC configuration control. The first major category is in design data base management.

We recommend analyzing the vendor manual or automated support for design configuration management to determine to what degree you can assume integrity of design information generated with a vendor's tool.

Design Data Base Management
The files used and created by ASIC tools constitute the design data base. A tool set containing a data base management tool that automatically tracks changed files in a single place is highly desirable. This tool proves vital for sharing files when developing a large design with multiple designers, and for correctly assembling a design package when a the vendor receives a design for layout and manufacture.

End-Item Data Package Format Analysis
High-reliability test and screening of ASIC devices produces massive amounts of information that normally receives further customer analysis. This information forms an "end-item data package." The form of information in this data package can greatly influence the cost of its analysis. Make sure that the vendor can deliver the end-item data package in a format that the customer can cost-effectively analyze.

Vendor Tool Support and Training

Vendor support of their tools is vital to the ASIC development program.


This is an essential service of an ASIC vendor. The complex process of mapping of a customer design into a working chip requires establishing a good dialog between vendor and customer engineers.


The ASIC vendor must provide the design team with training. Even with training, the learning curve on a vendor's cell library, not to mention their design tool set, is long and expensive.

The ASIC program manager should consider participating in at least some of the vendor's training. This training can give the manager invaluable insight into important control points in the vendor's ASIC development and test flow.


The complexity of an ASIC program demands clear and comprehensive documentation. To successfully complete ASIC tasks the vendor must have both hard copy and on-line reference information that is well organized, easily accessed, easily understood, and complete.


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