NASA Office of Logic Design
A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.
The NASA ASIC Guide: Assuring ASICs for SPACE
Chapter Four: Design Library Analysis
Objective:To outline major considerations for evaluating a vendor's logic cell library and related library tools.
A design library is a collection of cells representing logic structures and certain parametric structures that designers use to implement the functions of their ASIC. The economic and efficient accomplishment of ASIC design work depends heavily upon the choice of a design library. To help designers meet design goals, we advise the evaluation team to analyze the match between the vendor's technology and the design requirements.
Performing a thorough analysis will ensure that the library contains all the necessary elements for the required ASIC function and performance. We recommend that the team consider the following factors when evaluating a design library.
Function and PerformanceMake sure you verify that the cell library meets the function and performance requirements of a design, by reviewing a list of primitive, or basic cells, and macrocells from the vendor. 'Primitive' usually refers to simple logic cells such as NAND, NOR, FLIP-FLOPs, LATCHES, BUFFERS, and INVERTERS. Macrocells, also called 'megacells' or 'supercells,' offer diversified function and range from a shift register to a complex micro-processor.
There are two types of macrocells, hard and soft. Soft macrocells are functions comprised of primitive cells, which are placed and routed along with the rest of the chip. No cell layouts exist for the soft macrocells. Designers can configure soft macrocells at the time of instantiation. For example, an N-bit binary counter soft macrocell may include the following options:
- number of bits
- SEU immunity
- serial scan
- parallel load
- up and/or down count
Hard macrocells implement functions using custom design, usually to achieve better performance and transistor densities. The vendor tests and verifies both the hard macrocell layout and its function. Standard cells usually use hard macrocells but in some special cases gate arrays may also use them. A hard macrocell provides speed improvement over a functionally equivalent soft macrocell. Thus the hard macrocell occupies less area.
When evaluating a vendor, the function and performance of a vendor's cell library play a very important role. Macrocells are big time savers. If a vendor has a desired macrocell available, that can mean a more efficient design and considerable time saving. Designers should list the desired functions they plan to use in a design. The evaluation team can then compare this list to the functions offered by a vendor's design library.
Case Study: In selecting an ASIC vendor for the Cassini project AACS subsystem, JPL sought a vendor with a macrocell for Manchester encoder/decoder, which was a functional requirement for the ASIC. Managers knew that fulfilling encoder/decoder requirement with a macro would save considerable design time.
Testability"Selecting a vendor whose technology closely matches the design requiremnets helps the designers in meeting their design goals."
To economically support the test methodology of a design such as scan-based design, the cell library must have the appropriate cells. It is usually possible to implement a test approach using primitive cells, however, the additional time and gates required make this an uneconomical approach. Therefore, the evaluation team should make sure they evaluate the vendor's cell library for test features.
Although a vendor may have a large number of macrocells, some of the cells may not support the vendor's chosen testability approach. The evaluation team should make certain that all the cells in a design library support the vendor's methodology for testing ASICs.
If a vendor supports a scan design methodology for design for test (DFT), then make sure the design library has the following features available:
- All the sequential logic cells have the scan input, scan output, and scan control logic
- All I/O pads support boundary scan (IEEE 1149.1)
- Some support logic (macrocell) for built-in self test, boundary scan, internal scan, and test interface
The vendor may support a tool for automatically generating stuck-at fault test vectors, also called "automatic test pattern generation" (ATPG). If available, the evaluation team should review this capability, for:
- Design constraints -- What are the limitations in cell types and design approaches?
- Maturity of the ATPG tool -- Is it a real product, or is it just a "one-of" design, still needing massive bug fixes and constant support?
- Test vector formats -- Does the ATPG tool produce test vectors in a format that will work with both your CAD tools and the vendor production tester?
Radiation ToleranceCells for the majority of space applications need radiation tolerant design. Using different processing techniques and various design considerations the vendor can eliminate or minimize the radiation effects on circuit performance. Section Three: Chapter 4: "Design for Radiation Tolerance" discusses these alternatives in detail.
For radiation tolerant design, the evaluating team needs to verify that the vendor offers the following features in his design library:
- Pre-radiation and post-radiation timing and delay properties for all library cells available for the required level of total dose radiation (TID) and for threshold voltage shifts due to TID.
- There is no the possibility of latchup.
- The library provides SEU hardened storage elements, such as flip- flop, latches, register, RAM, etc.
- The cell library's target process is TID-hardened.
Model VerificationThe team should check that the vendor has verified simulation models of the design library cells. This means that the model values have been checked against measured device values. Among other checks, the cells should be examined for:
- functional correctness
- best and worst-case timing
- temperature and voltage derating
- delays due to capacitive loading
MIL-STD-883 mandates that manufacturers have a test chip to verify performance characteristics of the library cells. To conform with this standard, the vendor must have verified all setup, hold, minimum cycle time, enable and disable times provided with simulation models, through either circuit simulation or parameter extraction from actual hardware tests. The library analysis must include verification of the software-based library against the structures as actually built.
We suggest the evaluating team examine whether a macrocell has been implemented in silicon and verified for functionality and performance limits via actual hardware tests or whether the vendor's policy calls for only verifying the macrocell through software simulation.
The team also needs to determine what model levels the vendor has available for test and verification (characterization) of library cells. Examples of these model levels are:
- register-transfer level (RTL)
The levels used for evaluation tell the evaluation team how thoroughly the vendor checks new cells before bringing them into his libraries and the chances of a problem developing because of a difference between cell models and the cell as built. Ideally, all levels are examined for correct function and parametric performance before a cell joins a library.
Control and MaintenanceThe evaluation team should confirm that the vendor maintains and controls the design library with adequate configuration management. Configuration management at the least includes the following:
- cell library version control
- cell library upgrade control
- a thorough procedure and clear requirements for characterizing new cells before they become part of a library
- trouble tracking reports
- notification policy for major and minor changes to cells, related tools, and related processes (Internal groups should be notified so they can coordinate change effects from their perspectives and external groups (users, etc.) should be notified if cell changes may affect the designs)
DOCUMENTATIONThe team must see that the vendor keeps documentation on the use and application of design cell libraries current and complete. We suggest that the vendor provide document upgrades as soon as a change or modification occurs; the team might check that the vendor does this routinely according to the above notification policy discussion.
The team should examine evidence showing the vendor has verified all the specifications in the library data book. The team should also examine the vendor's actual use of regular regression testing to ensure new problems have not occurred and old problems have not crept back. All the tests and test results must be available upon request.
The cell library data book, at minimum, should provide the following information:
- setup and hold times
- minimum cycle time, enable and disable time
- library cell symbol with pin names and signal flow direction
- truth table for small/medium complexity cells
- theory of operations, RTL descriptions and other functional information for complex macrocells
- timing diagrams and other parametric information for complex macrocells
- operating range of temperature and voltage
- pre- and post-radiation propagation timing delays
- fan-in and fan-out
- variation of timing due to temperature and voltage
- approximate number of equivalent gates in each library cell
- approximate number of equivalent gates in each SEU hardened cell
- approximate number of equivalent gates in each scan cell
Some vendors provide a user's manual for the library. This manual helps designers by furnishing techniques for designing reliable ASICs and designing for performance and density.
- The evaluation team should analyze the match between the vendor's technology and the design requirements.
- To support the test methodology of a design, the cell library must have the appropriate cells.
- Cells for space applications quite often need radiation tolerant design. Check that the vendor has verified simulation models of the design library cells for functional correctness, along with the best and worst-case timing.
- Confirm that the vendor maintains and controls the design library through configuration management.
- Confirm the vendor has an excellent methodology for introducing new cells into the cell library you will use.
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