NASA Office of Logic Design
A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.
The NASA ASIC Guide: Assuring ASICs for SPACE
Chapter Three: Process Technology Analysis
Objective:To provide the evaluating team with guidelines to ensure that the vendor's ASIC technology can handle the design complexity, radiation hardness, and testability requirements of a space ASIC program.
Many requirements drive selecting a process technology. Variables include maturity, stability, radiation hardness, power consumption, transistor switching speed, and minimum transistor size. In reviewing process technology, we suggest that the evaluating team look carefully at the ASIC requirements compared to the vendor's process capabilities to determine if a process is adequate for an ASIC program.
The guidelines set forth in this chapter call for the evaluating team to clearly understand the designer's requirements that are essential to the successful completion of the project. Only then can they adequately review the vendor's offerings for process technology and match it carefully with the design requirements. Because of the complexity of selecting process technology, we advise the evaluating team to keep the design team well informed on all meetings through each step of the process.
The success of first pass silicon depends, among other factors, upon the right technology selection, and using certified design libraries. This chapter discusses three major considerations:
- choosing the ASIC technology
- ASIC design trade-offs
- verifying that the chosen technology can handle the design complexity
ASIC TechnologySelecting a vendor whose technology closely matches the design requirements helps the designers meet their design goals. The project normally determines the type of process technology, such as Silicon or GaAs, and the type of transistor implementation, such as complementary metal-oxide semiconductor (CMOS), emitter-coupled logic (ECL), or transistor-transistor logic (TTL). Within a particular type of technology, the vendor may offer different transistor sizes such as 1.0 um technology or 1.5 um technology, with different speed and electrical characteristics. Some vendors offer special processes, such as silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) to eliminate or reduce the possibilities of latchup due to radiation. The project details the ASIC operating conditions or ASIC specific technology requirements. The vendor should provide all the necessary data to review the process maturity, stability, and radiation hardness. If the potential vendors are government qualified, then the data are also available through the qualifying agencies.
ASIC Design Trade-Offs
"The success of first pass silicon depends, among other factors, upon selecting the right technology and using certified design libraries."
Most vendors offer both gate array and standard cell for their ASICs. In standard cells the vendor has customized each cell to give the maximum throughput, whereas in gate arrays the transistors occupy fixed slots and wire routing provides the required function. Therefore standard cells can offer better performance over gate arrays. For high volumes, standard cells are cheaper than gate arrays. For low volumes and fast turn- around time, gate arrays are more suitable. The non-recurring engineering (NRE) cost for gate array ASICs is less than standard cell ASICs.
Since ASICs can be developed as standard cells or gate arrays, we recommend that you base technology selection on design trade-offs. Table 2.3.1 illustrates the design trade-offs among these two categories.
Table 2.3.1 Gate Array vs. Standard Cell
A standard cell design requires a complete new set of masks for each design. A gate array starts with a base wafer that has already has several mask layers completed.
To make a design trade-off between gate array and standard cell ASIC, obtain the following information from the manufacturer:
- total gate count
- maximum usable gate count
- available I/O count
- available package size
- configuration of gates : Channel arrays or Sea of Gates
- percentage of process steps complete in base wafers
- maximum die size and the approximate number of gate counts in each die size
- available I/O count
- available package size
- available macro cells
GATE ARRAY AND STANDARD CELL
- NRE costs
- design turn-around time
- list of design macros
PackagingCompare the vendor's offering of the packaging to the design and project requirements. The different types of packages normally used are pin grid array (PGA) and surface mount with ceramic materials. Design requirements include the pin count and size of package. Review the thermal and electrical properties of packaging materials according to speed, noise, and reliability considerations.
RADIATION TOLERANCERadiation effects cause three major problems with ASIC microelectronics:
- charged particle induced single-event latchup (SEL)
- charged particle induced single-event upset (SEU)
- performance and parametric degradation through total ionizing radiation dose (TID)
The following suggestions will help avoid major problems:
Because latchup destroys most circuits, a vendor should offer a technology with "no-latchup." Hardening the storage elements of the design can obtain SEU immunity, or, the vendor can supply SEU hardened storage elements. A designer can utilize techniques, such as triple-modular redundancy (TMR) that to further increase the SEU hardness of a design, but this requires a significant increase in gates.
TID radiation can cause circuit performance degradation. Therefore, the vendor's design tool kit and cell library should support designing for the necessary radiation tolerance. A manufacturer should provide the timing margins for radiation in the cell library; the designer is responsible for designing his circuit within the margins. Section Three: Chapter 4 gives a detailed discussion of design for radiation tolerance. Appendix Three discusses the underlying physics of radiation effects on ICs.
The evaluation team must gather information from the vendor about the costs of their supported design for radiation tolerance. The vendors should supply information concerning:
- ratio of hardened to unhardened circuit sizes for circuits similar to your ASICs
- increased power consumption for hardened circuits
- decreased performance when using supported radiation hardening techniques
- special design rules for radiation hardening (fan-out limitations, etc.)
- packaging considerations
TESTABILITYThe manufacturer should offer a test methodology that allows a designer to economically satisfy project test requirements. A typical test requirement is 99 percent stuck-at fault coverage. Several design-for-test techniques help achieve this level of stuck-at fault test coverage. These techniques include full scan design, partial scan design, level sensitive scan design (LSSD), and boundary scan design. Section Three: Chapter 3 details these tests.
All parties must agree upon a test methodology from the start. Choosing a test approach in the middle of design may cause design delays due to learning new tools; it may even require redesign to satisfy the test approach. Vendors that can supply tools for the automatic generation of tests offer a clear advantage for economically producing a test.
The evaluation team must gather information from the vendor on the costs of these test approaches. Make sure the vendor and the designer understand the overhead associated with these test techniques. The vendors should supply information on the following:
- additional chip area or gate count required when using supported design for test (DFT) techniques in circuits similar to your ASICs
- decreased performance when using supported DFT techniques
- special design rules for supported DFT approaches (synchronous design, static design, no latches, etc.)
- support of test standards, such as IEEE 1149.1 Boundary Scan, etc.
- package/pin count overhead for test I/O, etc.
Wants Versus NeedsThroughout the process technology evaluation, the evaluating team must differentiate between designer preferences and the process technology essential to the project. Keep the designer and vendor informed on the outcomes of all meetings. Clear communication among all parties during process technology selection definitely saves design time at the end.
- The evaluating team must look carefully at the ASIC requirements compared to the vendor's process capabilities to determine if a process is adequate for an ASIC program.
- The evaluating team needs to keep the design team well informed on all meetings through each step of the process.
- Selecting a vendor whose technology closely matches the design requirements helps the designers meet their design goals.
- For high volumes, standard cells are cheaper than gate arrays. For low volumes and fast turn-around time, gate arrays are more suitable.
- If any radiation environment is anticipated for an ASIC, a vendor should offer a technology with "no-latchup" and with proven TID performance to the level your device will experience.
- The manufacturer should offer a test methodology that can satisfy project test requirements.
- The vendor must supply overhead information for both design for radiation tolerance and design for testability.
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