NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


Please e-mail comments and suggestions for these guidelines and criteria.

Design Guidelines and Criteria

for

Space Flight Digital Electronics

Miscellaneous Design Guidelines and Criteria

Noise Immunity and Quiet Designs: Take steps to ensure adequate and robust noise immunity.

Defensive Design and Designing for Off-Nominal Events: Consider credible but unplanned events.  Often many of these situations can be economically handled with a bit of thought.  Here are a few sample issues to consider.

Various Tips, Considerations, and Criteria

References, Notes, and Related Documents

  1. Note the drain wire attached to the lid of the FPGA (lower left hand corner) of the MOLA-2 PC-2 Electronics which is orbiting Mars on Mars Global Surveyor.  Conductive epoxy was used.

  2. The gold trace coming from only one corner of the lid identifies Pin 1 on this Virtex FPGA.. The manufacturer cut through the trace prior to the delivery leaving the lid floating, based on some customers' inputs.   We requested the opposite to ensure that there will be no buildup of charges and thus prevent ESD events.  Here is the cut, in a magnified view.

  3. OLD News #11 Interface Components and ESD, May 28, 2003.  ESD and proper device handling practices are nothing new and normally would not warrant an OLD News posting.  Indeed, ESD practice and component tolerance have improved so much over the years that ESD damage hasn't been a major source of problems for quite a while, for regular digital integrated circuits and interface components. However, there have been some recent surprises. ...

  4. The specifications for inputs must be carefully read as not all device or MCM inputs are truly TTL compatible.
  5. "Case Study: Simultaneous Switching Outputs," presented at "Design Seminar on Actel SX-A and RTSX-S Programmed Antifuses," Tuesday, April 13, 2004, NASA Goddard Space Flight Center.  Presents 4 cases of "staggering" I/O switching, trading off lower di/dt for increased data transfer time and analyzes software performance and the effect of module placement.

TOP LEVEL: "Design Guidelines and Criteria for Space Flight Digital Electronics"


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Last Revised: February 03, 2010
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