NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


"TTL Compatible" Inputs in CMOS Devices

All inputs in CMOS devices are not always truly TTL compatible.  To meet this criteria, VIL must be = 0.8V and VIH must be = 2.0V.  Data sheets and specifications must be read carefully to ensure that there will be proper noise margins.  Several examples are given below.


One example of this are the radiation-hardened CMOS devices designed and built for the Galileo project and also used by Magellan.  The intent of this development was to obtain pin-compatible replacement for existing bipolar device and to solve the SEU susceptibility issues for deep space missions.  However, as seen below, the devices were not truly compatible, requiring various circuit changes to ensure proper noise margins.

Variation of Vih over burn-in and life tests.  Data does not "track" and inputs are not TTL compatible, with Vih exceeding 2.0 volts.

This data set is from December, 1985.  Here are the key points:
  1. The histogram shown above is based on VIH measurements for the worst case pin in the post burn-in and post 2000 hour data for the "superspares" of SA2901, SA3227(2909) and SA3268(9407) devices.
  2. The average of the absolute values of the deltas for the superspares is 0.035 volt or 1.44%.
  3. Average VIH was 2.429 V post burn-in and 2.405 V post 2000 hours.

Example of an EEPROM MCM.  This device is organized in 2 rows of 4 devices with each microcircuit having a 128k x 8 organizations.

A second example are certain non-volatile memory modules assembled with commercial die.  The previous example is now almost 20 years old and is dated.  Today's manufacturers have solved their TTL compatibility problems and truly TTL compatible devices are now the norm and are in general expected.  However, this is not always true.  This example highlights a contemporary device that has been misapplied by several organizations.

For one project, three of a certain type of module were used with each module comprising 8 devices, organized as 2 rows of 4 devices.  Each device was a commercial Hitachi memory device.  The signal of interest here -- and the most critical signal for this device -- is the RES* pin, which provides protection for the device's contents during power transitions and transients and is controlled by the user.  One side effect is that when RES* is asserted not only are inadvertent writes blocked by the device can not be accessed for reads.  So, requirements are two-sided for this pin:

  1. Ensure that RES* is asserted so that the non-volatile memory device's contents are protected during power transitions and transients
  2. Ensure that RES* is not asserted during operations so that read operations may be performed.

A close reading of the data sheets shows the following key characteristics

  1. The VIH for most pins are not TTL compatible as this is specified as 2.2V, not 2.0V.
  2. The VIH for the RES* pin has a separate specification of VCC - 0.5V (4.5V under nominal conditions).
  3. IIH for the RES* pin is also special, with a value of 100 A.
  4. Input capacitance is 6 pF (max) per microcircuit pin.

Thus, the RES* pin which is not TTL compatible must be handled carefully.  Several organizations designed systems, comprising multiple cards, with three of the above modules, passively pulling up the RES* pin with a 1 kohm resistor.  The pin was asserted and well-driven for protection.  However, while there was focus on protecting the contents of the device, the opposite case of operating the device was not subject to a worst-case analysis.

First, although the RES* pin is a single pin per module, it is not buffered.  So the circuits interfacing to this board see a pin with the following characteristics:

The first implication of these atypical parameters is a large time constant for the RES* pin to be released.  A coarse and slightly liberal estimate for this is 2.2 time constants, which represents the time to go from 10% to 90%, with VIH being 90% of VCC and VCC = 5.0V.  So, in this case, we have 2.2 x 103 ohms x 200 pF ~ 0.5 s.  This is not normally a problem at the system level.  However, at the circuit level, this slow rise time will exceed the input transition time specifications for many devices which may result in unintended oscillations.

The second implication is more serious.  For zero noise margin, we would have a drop of 500 mV across a 1 kohm resistor which corresponds to a current of 0.5 mA.  However, we have a worst-case leakage of 2.4 mA just for the memory modules showing that this circuit will not meet a worst-case analysis based on device specifications.  Indeed, the analysis shows that this pin should be driven high (not asserted) by a low impedance for proper DC and AC noise margins and carefully routed to not pick up noise, common in many systems.  Recovery time from RES* assertion is on order of 0.5 s.  This situation can result in hard to isolate system crashes as the RES* input may trip by a dip in the signal level while typical TTL compatible circuits, with a VIH specification of 2.0 volts and a typical value of 1.4V will continue operating.  Indeed, this has happened in real systems and is not a theoretical case.


A third example comes from a device designed and built for high-reliability, radiation-hardened applications, the Aeroflex UTMC Summit device for MIL-STD-1553B applications. 

As seen above, the VIH was not truly TTL compatible with a value of 2.2 V given in the device specification.

However, the clock inputs on this device is treated differently from all of the other digital inputs.  This is also frequently seen on microprocessors and must be carefully driven.  In this case, VIL for the system clock is specified at 30% of VDD and VIH is specified as 70% of VDD with VDD nominally being 5.0 volts.  Obviously, devices that can not drive to the full 5.0 volt CMOS level will not be compatible with these inputs.  Many modern devices have a maximum voltage on their I/O buffers of only 3.3V, resulting in a negative noise margin.  Care of drivers, oscillators, etc. is warranted.

The TCK pin (JTAG 1149.1 test clock) is also called out separately with a VIL of 0.7V instead of the standard 0.8V.

This type of specification is often typical for clock inputs for devices of this nature, microprocessors, etc.


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Last Revised: February 03, 2010
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