NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


The NASA ASIC Guide: Assuring ASICs for SPACE

Chapter Two: Resource Planning

Objective:

To provide ASIC managers with a guideline to allocate the time, personnel and materials necessary to deliver ASIC flight parts on schedule and within budget.

The magnitude and complexity of ASIC programs for space applications demand careful planning and judicious use of resources. We encourage you to invest the necessary time in this primary task. Throughout your planning process remember that the reliability, radiation and testing requirements unique to producing space parts will influence all segments of your planning. Also, pay particular attention to the four major bottlenecks encountered in an ASIC program: simulation (verification), test vector generation, system integration (evaluation in a system environment), and part screening. Comprehensive planning of resources helps eliminate ad hoc solutions and ensures a smooth flow of the program.

To develop the most cost effective and time efficient use of resources, build your plan around each of the major ASIC tasks set forth in the first chapter of this section. The tasks are: set requirements, ASIC trade-offs, vendor selection, partitioning, ASIC implementation, physical layout, manufacturing, test and characterization, and part acceptance.

The following is a list of steps to follow when assembling a management plan for ASIC activities:

We will present schedules for the following high-level ASIC tasks, each broken into a number of sub-tasks:

We then present a schedule of major ASIC activity synthesized from those used in ASIC programs for the Cassini mission at JPL. Gleaning from all this information and considering his group's experience in various aspects of ASIC work, the ASIC manager can then synthesize his or her own ASIC schedules.

ASIC Vendor Evaluation

As discussed in Chapter 1 of this section, we recommend completing the ASIC vendor evaluation after determining the initial requirements for all ASICs in a project or system. (See Table 1.2.1).


Table 1.2.1 ASIC Vendor Evaluation

ASIC Design

The time for ASIC design activity varies, depending upon the design team's experience in ASIC design and in particular technologies, such as the type of cell library, type of process, etc. Design activity time also depends upon design complexity along with other requirements, such as testability and performance. A few rules of thumb will help guide you through this decision-making process. Plan for 3k to 5k gates per person, per month when doing a gate-level design. The numbers vary widely when using synthesis tools. It appears that gate-level synthesis does not yet shorten design time, unless there is a system-wide commitment to the identical synthesis tools and the approach. However, gate-level synthesis may increase reliability when done correctly, thus improving other aspects of the design process. (See Table 1.2.2).


Table 1.2.2 ASIC Design

Using standard cells versus gate arrays will generally have major differences for the following reasons:

ASIC Fabrication

To make sure you meet your ASIC time schedule, we recommend that you tie the vendor to a fabrication schedule by including it in the ASIC contract. We strongly advise that negotiations consider the time schedule as well as cost. For example, a gain in the fabrication time schedule may justify the increased cost of using a "hot lot" option--ASIC wafer lots given priority in a fabrication facility--especially when problems have delayed the work elsewhere. Check the vendor's flexibility to accommodate such needs. (See Table 1.2.3).


Table 1.2.3 ASIC Fabrication

ASIC Part Acceptance

Part acceptance depends heavily on the requirements of your project. If the project requires full QPL or QML devices, then part acceptance is relatively fixed. The only major exceptions relate to whether or not the space-specific appendix of the QML specification is invoked.

Remember, part acceptance activity calls for reviewing data from testing and screening to determine the device's suitability for a particular application. This means the part should not only meet the required functionality and performance but also show evidence of reliability in the intended application. (See Table 1.2.4).


Table 1.2.4 ASIC Part Acceptance

Equipment and Tool Planning

Equipment and tools take extensive planning for space ASICs. As the complexity of a device increases, so does the need for equipment and tools to ensure the parts meet the requirements. Commercial ASICs do not undergo the radiation and reliability tests required of a space flight part, making equipment and tool planning a simpler process. Off-the shelf parts require less testing, and therefore less equipment and fewer tools, because data already exists on the parts. The next section, Vendor Evaluation, describes the selection process for equipment and tools in detail.

An inventory of tools and equipment will tell you what you need to buy. However, before purchasing consider the ever changing market of equipment. When counting on available tools or equipment, the time factor becomes critical. Make sure the equipment will be available within your required time frame; simulators, testers or any other resources may be put in place but they may be tied up when you need to use them.

Consider all aspects of the ASIC program to determine any overlap. Carefully look at design, test, manufacturing, failure analysis, characterization, and screening, before purchasing new hardware and tools in the following areas:

Take care not to over buy equipment such as workstations and CAE tools; they are evolving so fast that they only have a typical lifetime of three to four years. Consider future upgrades and keep maintenance in mind when preparing a budget for tools and platforms.

Also, the choice of design methodology has great implications on workstations, design capture, and verification tools. Because of the tremendous number of variations from vendor to vendor, we cannot discuss the trade-offs of buying bundled or unbundled tools with platforms. We suggest managers analyze needs to determine the best packages for your ASIC work.

Workstations, mainframes, and PCs with tools installed from one or more CAE companies may be used for the following tasks:

For manufacturing, test, failure analysis (F/A), characterization, and screening consider the following:

In the above list, we have covered tools and equipment for all possible aspects of an ASIC program. A particular program may only require a subset of these lists. Check that tools are portable and interoperable before purchase. Also check for standardization.

When using a vendor's megacells, make sure the vendor's standard tool set supports them and that this tool set is used in-house. Some vendors may only support megacells through their design centers. Contracting with a third party to do ASIC designs can relieve many of these tool responsibilities at the cost of creating and sticking with an excellent ASIC device specification.

Personnel Planning

The unique nature of ASICs makes it imperative that you find personnel with the appropriate skills for the task; generally this means they must have experience with ASICs. For example, a team responsible for commercial ASIC design must have logic design and design simulation methodology skills. For space ASICs, a design team must also be cognizant of the radiation, reliability, and testability aspects of designing for the rigorous requirements a space part must meet. Specification writing, design verification, physical layout, the chip sign-off process, and ASIC verification at the system-level are also skills an ASIC team must possess.

INTERNAL PERSONNEL

"The ASIC management team needs to develop a working partnership with numerous groups and with several disciplines within NASA."

The heart of a successful ASIC is design. We recommend that designers have the following qualifications:

The magnitude and complexity of the ASICs will dictate the number of designers needed. Determining just how much one person can accomplish often proves a skill in itself. As discussed earlier, a few rules of thumb will help guide you through this decision-making process. Plan for 3k to 5k gates per person, per month when doing a gate level design. This number can vary depending upon the complexity of a design, familiarity with tools, and skill level of designers.

The following suggestions may help in planning:

EXTERNAL SUPPORT GROUPS

As an ASIC manager, you should get to know a number of groups and be ready to take advantage their expertise. A list of these groups and their associated ASIC support capabilities follows:

ASIC Center/Parts/Component Engineering Group:

CAE/CAT Group:

Procurement and Legal Group:

Failure Analysis Group:
You may find these services available within your organization. If they are not available, plan these services through an outside group or the vendor. Many NASA projects contractually require failure analysis capability to minimize the impact of failures. Failure analysis support includes:

Documentation Group:

Besides the groups described above, during various reviews you will likely work with groups such as an architecture group, a system- level implementation group, and a software development group.

A close working partnership usually develops between the vendor and various groups of your organization. As an ASIC manager, it is in your best interest to manage these relationships. You need to establish clearly the various points of contact, the task responsibilities, change and configuration control and other aspects of the relationship between your company and the vendor. Otherwise, there exists a real chance of the ASIC vendor receiving incorrect data and conflicting direction.

ASIC Program Budgeting

Producing ASICs for NASA introduces a new set of considerations for calculating budget expenditures. Even though you may be familiar with producing commercial ASICs, you will find that costing space ASICs differs enormously. Again radiation and reliability testing represent the major differences in budget. Commercial ASICs simply don't undergo this testing; commercial testing is included in design non-recurring engineering (NRE) charges or per piece pricing. When using off-the-shelf parts the vendor performs the radiation testing; design/process reliability has already been established.

As a manager of an ASIC program, you need to know where budget overruns commonly occur. Managers often overlook the cost of tools for discrete verification. They also may underestimate the NRE cost because they don't understand the elaborate testing costs. QML and QPL impose stringent test characteristics on the vendor, which the commercial producer does not have to abide by.

We will look at each of these individually to illustrate the cost characteristics unique to space ASICs.

TOOLS

The ASIC vendor's ability to supply as complete a solution as possible is the first point to consider about tools. Closely coupled with this is tool maturity. You do not want to pay for the debug of a set of tools new to an ASIC vendor with your engineers, your schedule, and your dollars.

As you evaluate your potential ASIC vendors (see Section Two), keep in mind the costs of sticking with any existing CAD tools you may already have; forcing the ASIC vendor's cell library and tools to work with them will almost always cost more in the long run than starting over with one of the ASIC vendor-supported CAD toolsets. Unfortunately, at present such miracle cures as design compilers for this classic problem, which may work for translating cell libraries from one CAD toolset to another, don't translate vendor tool functions at all.

As a rule of thumb, minimize the number of vendors needed to design and build your ASIC. Each vendor brings a new set of learning curves, maintenance, and new interfaces, all representing more costs and time. Since a mature ASIC vendor will have already done many designs with their in-house toolset, they are the first place to look for tools.

Remember, the design of an ASIC is one of the most challenging management of complexity problems engineers face. The choice of CAD toolset can help solve this problem or make it much worse.

PERSONNEL

"Costing space ASICs differs enormously from costing commercial ASICs."

Be careful not to underestimate the cost of personnel and support groups essential to producing space ASICs. They will consume a considerable portion of your budget. Take into account personnel that you may have to pay for, both on your ASIC team and from other parts of your organization, who perform or support the following:

VENDORS

The vendors will have some fixed and some variable costs. NRE charges represent fixed costs, which usually include physical layout and mask making charges. NRE also includes a limited number of prototype devices and limited central processing unit (CPU) time for any post-layout verification. Variable costs associated with engineering and flight parts will obviously depend upon the quantity requirements. You should consider the additional cost of having a vendor do any special custom macro design, custom package development, or test and characterization. Also consider anything that goes beyond their standard procedures, such as going through a place and route more than once, additional CPU time used on the vendor's mainframe, faster fabrication, and packaging services.

ASIC designers create the test vectors required for the chip sign-off process. Creating IDDQ test vectors may require translation from your workstation format to the vendor's format and from the vendor's tester format to a NASA center's tester format. These translations can result in significant cost.

Quality assurance, characterization, and screening are major cost components in the high reliability NASA arena. We identified support function costs from the personnel point of view previously. Some of these functions may be performed in part or jointly by the vendor, a NASA center internal parts group, or a third party.

The ASIC manager should allocate extra development costs to allow for the possibility that the program may incur one or more of the following: a second pass silicon; development of a new base array and its characterization; application specific tools; and doing a third party design as applicable.

Example Schedule

The following graphic contains a schedule synthesized from schedules created for a number of ASICs fabricated for the Cassini mission at JPL. They follow the assumptions set forth in the tables regarding vendor evaluation, design, fabrication, and part acceptance at the beginning of this chapter.

These schedules represent the first ASICs that JPL has done with a vendor. They also represent the first ASICs for most of the designers involved. As such, they reflect a typical first time ASIC schedule for any organization.

Note: JPL noted that the IDDQ work in items 54 through 61 of the following schedule detected significantly more defects than stuck-at fault testing. At this time, however, it is not clear how to quantify the reliability risks these defects represent. As a result of this and similar work, it is possible that IDDQ testing may replace some or all stuck-at fault testing.

Summary


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Last Revised: February 03, 2010
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