NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


References: Logic Design

 

Design Guidelines

Title, Authors, Reference, Link Abstract, Summary, Conclusions
Design, Analysis, and Test Guides A collection of guidelines, analysis, and documents to aid in the design, analysis, and test of spaceborne electronics and systems.


An Error Correction Code to Address Neutron Single Event Upsets in Semiconductor Memory

David W. Jensen, Ph.D.
Advanced Computing Systems
Rockwell Collins

Thirteenth Biennial Single Effects Symposium
Manhattan Beach, CA, April, 2002
jensen_rockwell_seesymp02.ppt


Introduction and Summary

  • Why concerned about Neutron Single Event Upsets (NSEUs)?
  • Error correction codes
  • Combining multiple mitigation techniques could enable an NSEU-tolerant, commercially-fabricated microprocessor
  • Presented efficient error correction block code to address Singe Event Upsets (SEUs) and Multiple Bit Upsets (MBUs) in semiconductor memory

Note: Could not make a .pdf file.  (May 3, 2002)

An Outline of Worst Case Analysis Requirements for Digital Electronics

WCA_Requirements.pdf

Abstract
     Every designer’s goal is mission success: the production of a correctly functioning system.  One of the keys to achieving that goal is the worst case analysis (WCA). A detailed WCA, if performed during the design phase, can find design problems that may not be found during the test phase. Timing errors, interface margin problems, and other design flaws may manifest themselves only under limited operating conditions that are not present during test, such as temperature extremes, age, or radiation, or in limited operating modes that are not exercised in test. The only way to guarantee that no design flaws exist in a circuit is to carefully analyze the circuit and prove their absence.
     The purpose of a WCA is to prove the design will function as expected during its mission. The spirit of analysis is proof: all circuits are considered guilty of design flaws until proven innocent. The following is an outline of WCA requirements which introduces the circuit design items that must be reviewed as part of the WCA.

Digital Timing Analysis Tools and Techniques

Timing.pdf

Abstract
     The timing analysis is a crucial part of a digital system’s worst case analysis. Every latched device has timing requirements -- set-up times, hold times, etc. - - that must be met in order to guarantee correct system operation, and the goal of the timing analysis is to determine whether they are met. Because each device input can have many sources whose timing can vary with circuit operation mode , the timing analysis can be very complicated and time consuming.  Thus many attempts at automating the timing analysis task have been made. But, the task is sufficiently complex that attempts to fully automate it have, so far, had only limited success. This report examines several timing analysis methods, and discusses their strengths and weaknesses.

Root-Sum-Square (RSS) Calculations of Digital Timing Delays

RSS.pdf

Abstract
     The subject of RSS versus extreme value calculations arises often in worst case analyses because the calculation of a quantity, e.g., the delay of a digital parts chain, required to be less than some value, will yield a smaller result when calculated by the RSS method than by the extreme value method, making it easier to claim that requirements are met.
     The validity of RSS is often debated without exploring its mathematical basis. This report discusses the basis for RSS calculations and the method’s limitations. Although the discussion is centered around calculating the propagation delays of digital circuits, the basic theory and conclusions apply to any application of RSS.


 

Design Assurance Guidance for Airborne Electronic Hardware

Radio Technical Commission for Aeronautics,
Committee: SC-180

Issued: 04/19/2000
DO-254

do-254.pdf
do-254.txt

Description
This document is intended to help aircraft manufacturers and the suppliers of aircraft electronic systems assure that electronic airborne equipment safely performs its intended function. The document identifies design life cycle processes for hardware that includes line replaceable units, circuit board assemblies, application specific integrated circuits (ASICs), programmable logic devices, etc. It also characterizes the objective of the design life cycle processes and offers a means of complying with certification requirements.

(May 19, 2002)
To obtain access to this document, you must obtain it from the Radio Technical Commission for Aeronautics.  It is a free download for members (NASA, for example, is a member).

Papers

A 400-MHz S/390 microprocessor

Webb, C.F.; Anderson, C.J.; Sigal, L.; Shepard, K.L.; Liptay, J.S.; Warnock, J.D.; Curran, B.; Krumm, B.W.; Mayo, M.D.; Camporese, P.J.; Schwarz, E.M.; Farrell, M.S.; Restle, P.J.; Averill, R.M., III; Slegel, T.J.; Houtt, W.V.; Chan, Y.H.; Wile, B.; Nguyen, T.N.; Emma, P.G.; Beece, D.K.; Ching-Te Chuang; Price, C.

IBM Corp., Poughkeepsie, NY, USA

IEEE Journal of Solid-State Circuits
pp. 1665 - 1675
Nov. 1997
Volume: 32 Issue: 11

Abstract:
A microprocessor implementing IBM S/390 architecture operates in a 10+2 way system at frequencies up to 411 MHz (2.43 ns). The chip is fabricated in a 0.2-/spl mu/m L/sub eff/ CMOS technology with five layers of metal and tungsten local interconnect. The chip size is 17.35 mm/spl times/17.30 mm with about 7.8 million transistors. The power supply is 2.5 V and measured power dissipation at 300 MHz is 37 W. The microprocessor features two instruction units (IUs), two fixed point units (FXUs), two floating point units (FPUs), a buffer control element (BCE) with a unified 64-KB L1 cache, and a register unit (RU).   The microprocessor dispatches one instruction per cycle. The dual-instruction, fixed, and floating point units are used to check each other to increase reliability and not for improved performance. A phase-locked-loop (PLL) provides a processor clock that runs at 2/spl times/ the system bus frequency. High-frequency operation was achieved through careful static circuit design and timing optimization, along with limited use of dynamic circuits for highly critical functions, and several different clocking/latching strategies for cycle time reduction. Timing-driven synthesis and placement of the control logic provided the maximum flexibility with minimum turnaround time. Extensive use of self-resetting CMOS (SRCMOS) circuits in the on-chip L1 cache provides a 2.0-ns access time and up to 500 MHz operation.

Index Terms:
CMOS digital integrated circuits; S/390 microprocessor; IBM S/390 architecture; CMOS technology; W local interconnect; instruction units; fixed point units; floating point units; buffer control element; unified L1 cache; register unit; phase-locked-loop; PLL processor clock; high-frequency operation; static circuit design; timing optimization; latching strategies; cycle time reduction; timing-driven synthesis; timing-driven placement; self-resetting CMOS circuits; 400 to 500 MHz; 0.2 micron; 2 to 2.43 ns; 2.5 V; 37 W; 64 KB; W

Circuit techniques in a 266-MHz MMX-enabled processor

Draper, D.; Crowley, M.; Holst, J.; Favor, G.; Schoy, A.; Trull, J.; Ben-Meir, A.; Khanna, R.; Wendell, D.; Krishna, R.; Nolan, J.; Mallick, D.; Partovi, H.; Roberts, M.; Johnson, M.;
Lee, T.

Adv. Micro Devices Inc., Sunnyvale, CA, USA

IEEE Journal of Solid-State Circuits
pp. 1650 - 1664
Nov. 1997
Volume: 32 Issue: 11
ISSN: 0018-9200

Abstract:
The AMD-K6 MMX-enabled processor is plug-compatible with the industry-standard Socket 7 and is binary compatible with the existing base of legacy X86 software. The microarchitecture is based on an out-of-order, superscalar execution engine using speculative execution. High performance and compact die size are achieved by using self-resetting, self-timed and pulsed-latch circuit design techniques in custom blocks and placed-and-routed blocks of standard cells. The 162 sq. mm die is fabricated on a 0.35-/spl mu/m, five-layer metal process with local interconnect. It is assembled into a ceramic pin grid array (PGA) using C4 flip-chip mounting. The processor functions at clock speeds up to 266 MHz.

Index Terms:
microprocessor chips; cache implementation; MMX-enabled processor; AMD-K6; microarchitecture; superscalar execution engine; speculative execution; self-resetting; self-timed circuit techniques; pulsed-latch circuit design techniques; custom blocks; placed/routed blocks; standard cells; five-layer metal process; local interconnect; ceramic pin grid array; ceramic PGA; C4 flip-chip mounting; CMOS microprocessor; 266 MHz; 0.35 micron

Circuit techniques in a 266-MHz MMX-enabled processor

Draper, D.; Crowley, M.; Holst, J.; Favor, G.; Schoy, A.; Trull, J.; Ben-Meir, A.; Khanna, R.; Wendell, D.; Krishna, R.; Nolan, J.; Mallick, D.; Partovi, H.; Roberts, M.; Johnson, M.;
Lee, T.

Adv. Micro Devices Inc., Sunnyvale, CA, USA

IEEE Journal of Solid-State Circuits
pp. 1650 - 1664
Nov. 1997
Volume: 32 Issue: 11

Abstract:
The AMD-K6 MMX-enabled processor is plug-compatible with the industry-standard Socket 7 and is binary compatible with the existing base of legacy X86 software. The microarchitecture is based on an out-of-order, superscalar execution engine using speculative execution. High performance and compact die size are achieved by using self-resetting, self-timed and pulsed-latch circuit design techniques in custom blocks and placed-and-routed blocks of standard cells. The 162 sq. mm die is fabricated on a 0.35-/spl mu/m, five-layer metal process with local interconnect. It is assembled into a ceramic pin grid array (PGA) using C4 flip-chip mounting. The processor functions at clock speeds up to 266 MHz.

Index Terms:
microprocessor chips; cache implementation; MMX-enabled processor; AMD-K6; microarchitecture; superscalar execution engine; speculative execution; self-resetting; self-timed circuit techniques; pulsed-latch circuit design techniques; custom blocks; placed/routed blocks; standard cells; five-layer metal process; local interconnect; ceramic pin grid array; ceramic PGA; C4 flip-chip mounting; CMOS microprocessor; 266 MHz; 0.35 micron

Skew-Tolerant Domino Circuits

Harris, D.; Horowitz, M.A.
Stanford Univ., CA, USA

IEEE Journal of Solid-State Circuits
pp. 1702 - 1711
Nov. 1997
Volume: 32 Issue: 11


Abstract:
Domino circuits are widely used in high-performance CMOS microprocessors. However, textbook domino pipelines suffer significant timing overhead from clock skew, latch delay, and the inability to borrow time. To eliminate this overhead, some designers provide multiple overlapping clock phases such that domino gates are always ready for evaluation by the time critical inputs arrive and do not precharge until the next gate consumes the result. This paper describes a systematic framework, called skew-tolerant domino circuits, for understanding and analyzing domino circuits with overlapping clocks. Simulations confirm that a speedup of 25% or more can be achieved over textbook domino circuits in high-speed systems.

Index Terms:
CMOS digital integrated circuits; skew-tolerant domino circuit; CMOS microprocessor; clock skew; latch delay; overlapping clock; simulation; high-speed system; pipeline; time borrowing


A Clock Distribution Network for Microprocessors

Restle, P.J.; McNamara, T.G.; Webber, D.A.; Camporese, P.J.; Eng, K.F.; Jenkins, K.A.; Allen, D.H.; Rohn, M.J.; Quaranta, M.P.; Boerstler, D.W.; Alpert, C.J.; Carter, C.A.; Bailey, R.N.; Petrovick, J.G.; Krauter, B.L.; McCredie, B.D.

IBM Thomas J. Watson Res. Center
Yorktown Heights, NY, USA

IEEE Journal of Solid-State Circuits
pp. 792 - 799
May 2001
Volume: 36 Issue: 5

Abstract:
A global clock distribution strategy used on several microprocessor chips is described. The clock network consists of buffered tunable trees or treelike networks, with the final level of trees all driving a single common grid covering most of the chip. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune such a large strongly connected interconnect network consisting of up to 6 m of wire and modeled with 50000 resistors, capacitors, and inductors. Variations are described to handle different floor-planning styles. Global clock skew as low as 22 ps on large microprocessor chips has been measured.

 

Books


Essential VHDL: RTL Synthesis Done Right

Sundar Rajan
1997 by Sundar Rajan and Gennis Piazza

Contents
  1. VHDL Basics
  2. Getting Your First Design Done
  3. Gates, Decoders and Encoders
  4. Registers and Latches
  5. Counters and Simple Arithmetic Functions
  6. Finite State Machines
  7. Reset, Preset, Tri-state and Bi-directional Signals
  8. Understanding Hardware Creation
  9. Design Partitioning
  10. Getting the Most from Your State Machines
  11. Scalable and Parameterizable Design
  12. Enhancing Design Readability and Reuse
  13. Creative Potpourri
  14. Simulation and Design Verification

Appendix A: Measuring Performance and Utilization


HDL Chip Design: A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs using VHDL or Verilog

Douglas J. Smith
1996 by Doone Publications
ISBN 0-9651934-3-8

Contents
  1. Introduction
  2. Synthesis Constraint and Optimization Tutorials
  3. Language Fundamentals
  4. Design/modeling Recommendations, Issues and Techniques
  5. Structuring a Design
  6. Modeling Combinational Logic Circuits
  7. Modeling Synchronous Logic Circuits
  8. Modeling Finite State Machines
  9. Circuit Functions modeled Combinationally of Sequentially
  10. Tri-State Buffers
  11. Test Harnesses
  12. Practical Modeling Examples

Glossary
Appendix A: VHDL
Appendix B: Verilog


Clock Distribution Networks in VLSI Circuits and Systems

Eby G. Friedman, Editor
1995 by the IEEE
ISBN 0-7803-1058-6

Contents
Preface
  1. Basic Concepts and Analysis
  2. Clock Distribution Design of Structured Custom VLSI Circuits
  3. Automated Layout and Synthesis of Clock Distribution Networks
  4. Analysis and Modeling of the Timing Characteristics of Clock Distribution Networks
  5. Specification of the Optimal Timing Characteristics of Clock Distribution Networks
  6. Clock Distribution Networks for Targeted VLSI/WSI Architectures
  7. Example Implementations of Clock Distribution Networks


High-Speed Digital Design
A Handbook of Black Magic

Howard W. Johnson
Martin Graham

1993 by PTR Prentice-Hall, Inc.
ISBN 0-13-395724-1

Contents  (detailed contents)
Preface
  1. Fundamentals
  2. High-Speed Properties of Logic Gates
  3. Measurement Techniques
  4. Transmission Lines
  5. Ground Planes and Layer Stacking
  6. Terminations
  7. Vias
  8. Power Systems
  9. Connectors
  10. Ribbon Cables
  11. Clock Distribution
  12. Clock Oscillators

Collected References
A. Points to Remember
B. Calculation of Rise Time
C. MathCad Formulas


Skew-Tolerant Circuit Design

David Harris, Harvey Mudd College
2001 by Academic Press
ISBN 1-55860-636-X

Excerpt from the Introduction:

Most digital systems today are constructed using static CMOS logic and edge-triggered flip-slops.  Although such techniques have been adequate in the past and will remain adequate in the future for low-performance designs, they will become increasingly inefficient for high-performance components as the number of gates per cycle dwindles and clock skew becomes a greater problem. Designers will therefore need to adopt circuit techniques that can tolerate reasonable amounts of clock skew without an impact on the cycle time. Transparent latches offer a simple solution to the clock skew problem in static CMOS logic.   Unfortunately, static CMOS logic is inadequate to meet timing objectives of the highest-performance systems. Therefore, designers turn to domino circuits, which offer greater speed. Unfortunately, traditional domino clocking methodologies [92] lead to circuits that have even greater sensitivity to clock skew and thus can defeat the raw speed advantage of the domino gates. Expert designers of microprocessors and other high-performance systems have long recognized the costs of edge-triggered flip-flops, and traditional domino circuits and have used transparent latches and developed a variety of mostly proprietary domino clocking approaches to reduce the overhead. This book formalizes and analyzes skew-tolerant domino circuits, a method of controlling domino gates with multiple overlapping clock phases. Skew-tolerant domino circuits eliminate clock skew from the critical path, hiding the overhead and offering significant performance improvement.


The Well-Tempered Digital Design

Robert B. Seidensticker
1986 by Addison-Wesley Publishing Company, Inc.
ISBN 0-201-06747-1

Excerpts from the Preface:

The practical side of digital design has received much less attention in the engineering curriculum than design theory.

This book is a collection of "proverbs"; each proverb describes an important piece of practical digital design knowledge.  The proverbs here are largely time-independent, ensuring that they remain relevant for years.  They are self-contained and logically categorized for ease of reading.  A thorough glossary and index make them easily referenced.  The book can be read from front to back, as a textbook, or can be referenced randomly, as a handbook.  References sections allow the interested reader to pursue topics further.


Switching and Finite Automata Theory

Zvi Kohavi
Departments of Electrical Engineering and Computer Science
TECHNION - Israel Institute of Technology
1978, 1970 by McGraw-Hill, Inc.
ISBN 0-07-035310-7

 


Digital Logic and Computer Design

M. Morris Mano
California State University, Los Angeles
1979 by Prentice-Hall, Inc.
ISBN 0-13-214510-3

 


Introduction to Switching Theory and Logical Design
Third Edition

F. Hill and G. Peterson
University of Arizona
1968, 1974, 1981 by John Wiley & Sons, Inc.
ISBN 0-471-04273-0

 


Analysis and Design of Digital Circuits and Computer Systems

Paul M. Chirlian
Stevens Institute of Technology
Matrix Publishers, Inc., Champaign, Illinois
1976

 


Fault Tolerant & Fault Testable Hardware Design

P. Lala
Syracuse University
1985 by Prentice-Hall, International
ISBN 0-13-308248-2

Table of Contents

Basic Concepts of Reliability
Faults in Digital Circuits
Test Generation
Fault Tolerant Design of Digital Systems
Self-Checking and Fail-Safe Logic
Design for Testability
Conclusion
Appendix: Markov Models


Application Specific Processors

Edited by Earl E. Swartzlander, Jr.
1997 by Kluwer Academic Publishers

Table of Contents
  1. Variable-Precision, Interval Arithmetic Processors
  2. Modeling the Power Consumption of CMOS Arithmetic Elements
  3. Fault Tolerant Arithmetic
  4. Low Power Digital Multipliers
  5. A Unified View of CORDIC Processor Design
  6. Multidimensional Systolic Arrays for Computing Discrete Fourier Transforms and Discrete Cosine Transforms
  7. Parallel Implementation of a Fast Third-Order Volterra Filtering Algorithm
  8. Design and Implementatin of an Interface Control Unit for Rapid Prototyping

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Last Revised: February 03, 2010
Digital Engineering Institute
Web Grunt: Richard Katz
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