"A Reconfigurable and Evolvable Hardware Fabric"

Chris Papachristou and Frank Wolff
Case Western Reserve University

Abstract

In this work, we are developing a novel reconfigurable multiprocessor architecture, environment and tools for autonomous onboard processing in space platforms. Among the important features of our method are: reconfigurability and processor adaptability for high rate wireless functions; usage of system-on-chip (SOC) technology to embed hardware modules and reconfigurable blocks; integration of real-time Operating system kernels on the SOC, low-power, quality of service, and performance.

Our approach employs a multiprocessor architecture consisting of the following layers: Layer 1, the recon-figurable hardware fabric. Layer 2, the embedded processors and memory modules. Layer 3, the real-time Operating system kernels (RTOS). Layer 4, the adaptation manager. Our approach is based on the twofold concept: adaptation of the application software coupled with dynamic reconfiguration of the hardware fabric. We achieve this by careful interaction and coordination of the adaptation manager and the reconfigurable fabric. The adaptation manager captures real time inputs from sensors and decides what reconfiguration, if any, needs to be performed and then sends this information to the hardware fabric which performs dynamic reconfiguration. The adaptation manager also involves a software learning process to correct adaptation and reconfiguration decisions. We employ middle level configuration granularity for rapid or dynamic reconfiguration implementing mission critical functions such as signal and imaging functions. We consider two alternative reconfigurable hardware platforms: a) Platform FPGAs (e.g. Virtex II); b) a new reconfigurable hardware fabric. Platform FPGAs integrate into a large FPGA structure microprocessor cores, ASIC blocks (e.g. multipliers) and memories. Platform FPGAs have the advantage of platform stability but they are not amenable to autonomous or self configuration. To alleviate these limitations, we are investigating a new reconfigurable hardware fabric and develop tools for incorporating the fabric into SOC. The Hardware Fabric is a distributed set of programmable processing tiles that are capable of instantaneous reconfigurability. A tile consists of three types of modules, i.e. function, local memory and local control modules. A programmable tile goes much beyond the current FPGA technology. A tile achieves middle grain configuration by efficiently allocating its resources, i.e. operator units and caches as well as their interconnects. Configuration occurs within a tile, and in several tiles that can be interconnected into a reconfigurable fabric. The Embedded Processors Layer integrates embedded DSP cores and memories. There are two roles for this layer: a) to support the adaptation manager and OS kernels. b) to provide processing capability for baseline functions that do not demand intensive computations. The Real Time OS kernel Layer coordinates activities of the other layers and the input/output. 

Status of work. Currently we have been working on the following challenging tasks. 1) Performed analysis, simulation and design of the architecture layers using commercial CAD tools. 2) Developed algorithms and tools for mapping application C models into the reconfigurable hardware. In the future we plan to develop a testbed prototype environment for applications demos.

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