"Microprocessors with FPGAs: An Implementation and Workload Partitioning Study of the DARPA HPCS Integer Sort Benchmark within the SRC-6e Reconfigurable Computer"
E. Allen Michalski and Duncan Buell
University of South CarolinaAbstract
Previous solutions to economical high-performance computing have been based on the use of COTS microprocessor-based workstations as compute nodes. The combination of traditional microprocessors and Field Programmable Gate Arrays (FPGAs) is developing as a platform for intensive computational computing. These “reconfigurable computers” combine the best aspects of traditional microprocessor front-end processing capabilities with the reconfigurability of FPGAs for computation-intensive problems, providing order-or-magnitude speedups versus software solutions alone. In this paper, we implement the DARPA HPCS integer sort benchmark on one of the leading prototype reconfigurable computers, SRC Computers’ SRC-6e. The hardware architecture and programming model of the SRC-6e is presented. FPGA implementation, timing and utilization results for integer bubblesort and parallel heapsort algorithms are presented, and PC/FPGA workload partition choices are discussed. For PC/FPGA workload partitions we discuss a time-to-solution hyperbolic minimization that indicates an optimal amount of data for FPGA processing, providing maximum processing throughput. Five partition cases that include PC-only, FPGA-only and PC/FPGA solutions are presented, with results indicating a combination of PC and FPGA processing to provide the fastest throughput. Conclusions regarding reconfigurable computing as a high-performance compute node are presented.