"Design, Development and Validation Testing of a Versatile PLD Implementable Single-Chip Heterogeneous, Hybrid and Reconfigurable Multiprocessor Architecture"
J. Robert Heath, Sridhar Hegde, Kanchan Bhide, Paul Maxwell, Xiaohui Zhao, and Venugopal Duvvuri
University of Kentucky
There appear to be an increasing number of real-time and non-real-time computer applications where the application may be described by process and/or data-flow graphs (from here on we use the term “process flow graphs”). A process is viewed to be a multiple instruction program, not a single instruction. Such applications include radar signal processing, sonar signal processing, various system simulation environments utilized within Computer Aided Design (CAD) software systems, communications signal processing, routing, control signal processing, etc. For such applications, a first goal is the availability of a computer system/architecture platform which will allow an application described by a process flow graph of any topology to be mapped to and executed on the computer system/architecture. The application process flow graph could be single or multiple input/output and cyclic or acyclic. Processes are represented by nodes of the graphs. Further, it would be desirable for the computer system/architecture to be able to continue execution of the application with minimum interruption if the application process flow graph topology were to dynamically change during application execution. This goal is referred to as application level reconfigurability. A second goal for the same computer system/architecture would be that it have the ability to dynamically on-the-fly configure, move, or assign processors or other physical resources to application processes (and/or vice versa, the assignment of additional copies of a process to additional stand-by processors due to processor overload or faulty malfunctioning processors) that may need them at any time. This goal is referred to as node level reconfigurability. A third goal for the same computer system/architecture would be that it be a single-chip heterogeneous multiprocessor system and that it would have the capability to dynamically on-the-fly configure and reconfigure, if and when needed, single processor architectures within the overall multiprocessor architecture. We refer to this goal as processor architecture level reconfigurability. With proper Operating System (OS) and other system software support, a computer system/architecture platform which can meet these three goals should be able to execute a wide range of non-real and real-time applications described by process flow graphs of any topology in a fault tolerant manner. It would be hybrid in that it operates in a data flow (control-token flow) mode at the process level rather than a single machine language instruction level. Control tokens flow through the architecture rather than more voluminous data.
The contributions and key points of this paper are in that it describes currently on-going research and development and current status of the design, development, testing and evaluation of such a computer system architecture. The organization, shared memory multiprocessor architecture and all its functional units are first addressed. Major functional units addressed include a new multifunctional Queue fronting each heterogeneous processor of the architecture, a dynamic hardware load balancing mechanism for the architecture, a processor to shared memory interconnect which implements a variable and dynamic memory contention resolution protocol, overall control token mechanism used for control of the architecture, shared RAM organization, heterogeneous processor organization/architecture requirements, etc. HDL (VHDL) “virtual prototype” functional and performance simulation testing results are shown for the architecture executing simple hypothetical applications. Testing results first reveal and illustrate the architecture can implement applications described by both cyclic and acyclic process flow graphs (application level reconfigurability). Testing results further reveal the architecture can currently implement node level reconfigurability as defined above. Future research, development and testing of the architecture is addressed. Focus of future research will be development of processor architecture level reconfigurability and identification of real applications (real-time and non-real-time) which may best run on the architecture. The described architecture paradigm and platform is known as a single-chip Hybrid Data/Command Driven Architecture (HDCA) system. A reconfigurable/dynamic production HDCA system would be implemented to Programmable Logic Devices (PLDs).
Key Words: Dynamically reconfigurable architecture, single-chip heterogeneous multiprocessor architecture, hybrid architecture, data or command driven architecture, hardware load balancing, Programmable Logic Device (PLD) implementation, virtual prototyping.
2005 MAPLD International Conference Home Page