"Reconfigurable Field Programmable Gate Arrays (FPGAs) for Space – Present and Future"
The capability to implement reconfigurable digital systems based on FPGA technology is a reality today. Reconfigurability is defined in a continuum ranging from rapid design development, post-deployment hardware modifications, through to runtime reconfiguration for processing and computing. In addition, designer are increasingly looking to FPGA-based computing as performance improvements of traditional Von Neuman processors begin to level off. These topics are of increasing interest to designers of Space-based systems.
Two emerging technologies, Rad Hard by Design (RHBD), and runtime Partial Reconfiguration (PR) will dramatically increase the efficiency and reduce the cost of using reconfigurable FPGAs in Space Applications.
Today, reconfigurable FPGAs are susceptible to Single-Event Effects (SEEs) which can corrupt the configuration memory and affect the user’s design. Reconfigurable FPGAs can be made virtually immune to SEEs through the use of Triple-Module Redundancy (TMR) and configuration memory scrubbing, although these techniques bring added PCB complexity and reduce the number of available logic cells. Efforts are underway to introduce RHBD FPGAs that will be immune to SEEs. FPGAs employing RHBD configuration memory will not require TMR or configuration memory scrubbing for protection against SEEs and will offer increased reconfigurable capability for field upgrades and runtime Partial Reconfiguration (PR).
Runtime PR offers a means for changing design modules on-the-fly, while the “base” design continues to operate uninterrupted. This allows multiple design modules to time-share the same physical silicon resources, thereby reducing device resource utilization, device count, and power consumption.
Partial Reconfiguration is available today, and will become increasingly important for space-based systems where PCB footprint, mass, and power consumption are of even greater concern. This paper will review the present and future state of commercial process technology, reconfigurable FPGA architecture, FPGAs for Space, and the benefits offered by PR and RHBD.
2005 MAPLD International Conference Home Page