"Single Event Effects Mitigation of a Soft Embedded Processor in the Virtex-II FPGAs"

Sana Rezgui1, Jeffrey George2, Gary Swift3, Kevin Somervill4, and Carl Carmichael1,

1Xilinx, Inc.
2The Aerospace Corporation
3
Jet Propulsion Laboratory / Caltech
4
NASA Langley

Abstract

The growing interest in using embedded system applications built on Static Latch Based FPGAs in space and the well-known upset sensitivity of these FPGAs in radiation environment, have led to many research activities for their upset mitigation in orbit. Among these activities, are efforts led by the North American SEE Consortium to test and mitigate a given embedded processor under irradiation, when implemented on a Xilinx Virtex-II FPGA. The objective of these studies is twofold: first to determine the impact of the proposed mitigation solution on the design performance and second to evaluate its effectiveness for creating a fully-mitigated embedded system to operate in a radiation environment.

In this paper, is presented a complete solution that targets specifically soft embedded processors operating on Virtex-II FPGAs to cope with transient faults in the user combinational and sequential logic. The proposed solution uses the Xilinx Triple Modular Redundancy (XTMR) tool to triplicate the user design resources, and provides for configuration scrubbing of the DUT internal resources to prevent the accumulation of induced upsets. The target processor in this study is the Xilinx MicroBlaze™ Intellectual Property (IP) soft core. Its implementation will be detailed in the final paper as well as the impact on the design performances (additional FPGA resources required as compared to that of the unmitigated design, frequency of execution and penalty in power consumption).

Radiation test experiments conducted to evaluate the effectiveness of the proposed mitigation solution were performed at the Crocker Nuclear Laboratory at UC-Davis using a proton beam of 63.3 MeV. The proton-induced error rate for the mitigated design is estimated to be lower than 1x10-9, which is lower than any SEFI cross-section (1x10-6), and successfully proves the efficacy of the TMR methodology applied to Virtex-II FPGAs in mitigating transient faults likely to occur in space applications. The experimental results will be reported in the final paper along with additional information on resource utilization tradeoffs vs. the level of upset mitigation achieved.

 

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