"Verification of Intellectual Property for FPGA Designs"
The usage of Field Programmable Gate Arrays (FPGAs) has become commonplace in Aerospace and Military electronics systems. The increasing sophistication and multi-million gate designs, are forcing designers to use pre-built Intellectual Property (IP) to build these System-on-a-Chip (SOC) FPGA designs. Unfortunately, there is often concern with using 3rd-party IP due to the perceived risks and lack of standards for producing IP. In reality, designers are often choosing to use pre-built IP for many standard functions because the IP is thoroughly used, debugged, and documented far beyond what a company can do on their own. To build quality, re-useable IP, requires a disciplined development process using synthesizable HDL cores, including multiple verification steps. Additionally, the IP should come with a host of environmental support to simplify the verification of the initial cores, the integration into the system and the verification of the system-level IP. A well-tested MIL-STD-1553 example is given that followed a phase-gate development process, was thoroughly tested and has an extensive heritage in military and aerospace customer applications.
2005 MAPLD International Conference Home Page