"Analysis and Reduction of Soft Delay Errors in CMOS Circuits"
Chris Papachristou, Balkaran S. Gill, Francis and G. Wolff
Case Western Reserve University
Soft errors in CMOS circuits are due to highly energetic particle strikes at the sensitive nodes. In this paper, we present a methodology to analyze a type of soft errors which manifests as Soft Delay Errors (SDEs) . A SDE occurs when a particle strike induced delay results in erroneous data latch-up. We propose a systematic approach for SDE analysis of CMOS circuits. A mixed-mode simulation technique is used to extract current pulses for the characterization of SDE. The extracted current pulses are then used to analyze soft delay on the critical path of the ISCAS85 benchmark circuits.
We define a metric to compute hot nodes in a circuit and describe a step by step procedure to compute it. The hot nodes are nodes of the circuit which are very sensitive to produce SDEs.
The hot nodes are determined based on the ratio of the number of errors appeared at the output(s) of the circuit to the number of transitions at the struck node. The number of errors that appear at the output(s) are divided again into two different categories: single error and multiple errors. The single error occurs when one or more errors appear at the output but considered as one error only. The multiple errors are based on how many errors appear concurrently at the outputs.
Nodes which are highly sensitive for SDEs are resized. The reduction in the number of SDEs is shown for an example circuit. In this case, 50% errors reduction was achieved by resizing only 33% of the gates of the circuit.
The advantage of using this approach is to resize only the gates which have hot nodes, not all the gates in the circuit. This technique is complementary to the existing glitch analysis techniques used for traditional soft errors in CMOS logic in the sense that they both provide comprehensive analysis.
B. S. Gill, C. Papachristou, and F. G. Wolff. Soft delay error effects in cmos combinational circuits. IEEE VLSI Test Symposium, pages 325–331, 2004.
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