"Impact of Negative Bias Temperature Instability on FPGAs"

Yuan Chen, Doug Sheldon, Ramin Roosta, Gary Burke, and Tien Nguyen
Jet Propulsion Laboratory, California Institute of Technology, Pasadena


This paper investigates negative bias temperature instability (NBTI) in FPGAs.

PMOS NBTI has become one of the key reliability concerns for CMOS circuits in recent years [1-2]. NBTI phenomena are observed when p-channel MOSFET transistors are subjected to “moderate” negative gate bias at elevated temperatures, typically corresponding to gate oxide electric fields of 1MV/cm to 5MV/cm. NBTI mechanism involves the generation of Si/SiO2 interface trapping, usually referred to as “donor-like” interface traps, and oxide charge. Holes are attracted to the Si/SiO2 interface and it weakens the Si-H bond until it breaks. Hydrogen diffuses into the oxide and leaves an interface trap. The NBTI process results in an increase in the absolute threshold voltage Vth, a decrease in the transconductance gm and an increase in absolute off current Ioff. It has been demonstrated that NBTI is the dominant degradation mechanism during static inverter stress for advanced CMOS technologies [3-4]. With an increase of the threshold voltage and a decrease of the mobility, the inverter propagation delay becomes larger. There is extensive literature available on NBTI from the device physics and process development point of view, but less information can be found in the area of correlating the transistor level NBTI degradation to the circuit performance and long-term reliability.

In this work, an inverter propagation delay function is used for PMOS transistor NBTI and FPGA circuit statistical analysis, demonstrating that the variation of the NBTI degradation is one of key factors to be included. An integrated series of experiments and reliability simulations based on possible NBTI induced propagation delay will be used to determine SRAM based FPGA performance and reliability. A design of experiment (DOE) approach will be taken to investigate propagation delay of ring oscillator test structures as well as buffer circuitry. Different frequencies, duty cycles, temperatures, and supply voltages designed to produce maximum NBTI stress conditions will be used. Timing path degradation and possible non-functionality will be correlated and discussed.

Key References

  1. C.E. Blat, et al, “Mechanism of negative bias temperature instability”, Journal of Applied Physics, 69, 1991, page 1712
  2. A.T. Krishnan, et al, “Impact of charging damage on negative bias temperature instability”, IEEE IEDM, 2001, page 865
  3. F.E. Pagaduan, et al, “The effects of plasma-induced damage on transistor degradation and the relationship to field programmable gate array performance”, IEEE IRPS 2001, page 315
  4. V. Reddy, et al, “Impact of negative bias temperature instability on digital circuit reliability”, IEEE IRPS 2002, page 248



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