"Reliability Analysis on the Aeroflex ViaLinkTM FPGA"
Aeroflex Colorado Springs
Aeroflex Colorado Springs will update the reliability analysis of the ViaLink based RadHard Eclipse FPGA. Modifications to the reliability flow and associated new testing have aligned the RadHard Eclipse analysis with the recommendations and concerns of the aerospace community. Data from the new test flows will be the focus of the presentation.
To orient users and gain perspective, test conditions for each phase of the analysis are defined. This begins with the preparations and conditions for un-programmed burn-in. Following are discussions on device programming, post-programming electric test, and device stress. Stress conditions are defined for temperature, voltage and time for both low temperature and high temperature operating life (LTOL and HTOL).
With analysis conditions defined, the resulting data is reviewed. This data includes yields from burn-in and life test as well as an analysis of any change seen during testing. Functional and electrical test along with programmer logs and ViaLink verification are used to inspect for auto programming. Current and AC delay path deltas from pre-stress baseline to post-stress characterization are used to analyze ViaLink deprogramming. Projections from testing to determine FIT rates for the RadHard Eclipse products are presented.
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