"An FPGA Based Processor for Hubble Space Telescope Autonomous Docking – a Case Study"
Jonathan F. Feifarek and Timothy C. Gallagher
Lockheed Martin Space Systems Company
Designing electronic hardware for flight projects typically requires balancing conflicting constraints: the architecture must have a stable configuration in a short period of time, be tolerant of radiation induced effects, work within a limited thermal dissipation environment, and be flexible enough to accommodate changing requirements or even in-flight updates. FPGA’s provide a way of balancing all these constraints.
NASA Goddard’s Hubble Telescope Robotic Reservicing Vehicle project necessitated a rapid turnaround customized flight solution to service the Hubble Space Telescope (HST) before aging critical components failed. A key component, autonomous rendezvous and docking, required processing throughputs that greatly exceed the capacity of any existing radiation hardened processor because of a need to process independent algorithms with different camera views in parallel. FPGA’s were determined to be the only viable solution to meet these processing constraints capable of providing the necessary update rate for the guidance, navigation, and control to accomplish low rate direct docking with the delicate HST.
Use of a HOL was considered the best way to realistically meet the difficult schedule of converting existing complex and specialized “C” vision code to synthesizable RTL for implementation on FPGAs. Other advantages of using a higher abstraction level of design is the ability to optimize and verify code orders of magnitude faster then RTL simulation, automating complex state machine control, and generating bit-accurate and cycle-accurate RTL output before porting to hardware.
To meet the high proton radiation environment within the cost and power constraints of the mission, a dual redundancy approach at the FPGA level was chosen taking advantage of the system’s tolerance for limited data dropouts but not for result uncertainty. The advantages of this design and its limitations are explored in this case study.
This paper discusses the challenges encountered in designing an algorithmic intensive FPGA based processor for flight and presents a case study to show how these difficulties were mitigated for the Hubble Robotic Vehicle.
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