"Design and Timing Closure Techniques for Managing Wide Semiconductor Timing Variations in Space Applications"
Alexander Osovets1 and Michael Cuviello2
1Orbital Sciences Corporation
2Michael Cuviello Muniz Engineering Inc.
Presented as a case study of a Radiation-hard, FPGA based micro-controller processing card, this paper illustrates how novel design techniques and an advance timing closure tool flow are applied to address the aspects of microelectronic performance often encountered in the design for high radiation environments. These are relaxed timing definition and timing drift of digital microelectronics due to the environment impact over the life of a mission.
In this case, the system was initially designed and analyzed as a single synchronous clock system. To compensate for the previous mentioned issues, reduced clock speed and added processor wait states were required to guarantee sufficient timing margin. As a result system performance was significantly impacted.
Consequently, the architecture is modified by dividing the system into multiple clock domains and implementing data synchronizers and glitch free control handshaking. This modification makes possible reliable cross correlated-phase-shifted domain signaling that addresses long-term pseudo-asynchronous variation and drift between clocks. In addition, an ASIC-like tool flow is utilized that includes hold-time verification and multiple mode, cross-domain, system level static timing analysis. This provides more accurate timing closure and eliminates the need for complicated manual analysis. The overall result is a system design with more robust timing margins and overall improved performance.
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