"Initial Single-Event Effects Testing and Mitigation in the Xilinx Virtex II-Pro FPGA"

J. George1, S. Rezgui2, G. Swift3, G.Allen3, C. Carmichael2

1The Aerospace Corporation
2Xilinx, Inc.
Jet Propulsion Laboratory, California Institute of Technology


SRAM-based field-programmable gate arrays (FPGAs) such as the Xilinx Virtex II and Virtex-II Pro series offer great flexibility in space applications. A consortium of industry and government partners has been evaluating the sensitivity of the “radiation-tolerant” Virtex-II FPGAs to single event effects. We have also tested the effectiveness of some common mitigation techniques that can be incorporated into real designs. A similar evaluation of the Virtex-II Pro device has begun and we will present the initial results.

The configuration logic blocks and block RAM cells were tested in a static mode by pre-loading a clean configuration. The configuration bitstream was readback after irradiation by heavy ions to determine the number of errors. The single event upset (SEU) cross section (per-bit) curves are very similar to those seen in the Virtex-II at high LET values but have a significantly flatter knee region that should result in lower on-orbit error rates.

We have also tested the FPGA in a dynamic mode by clocking data through the Input/Output Blocks (IOBs) to a set of counters at 33MHz. This effectively measures the sensitivity of an input/output pair, a common building block in many designs. The test compared an unmitigated design with a triple-modular-redundancy (TMR) mitigated version created with Xilinx’ TMRTool utility. Single-ended (LVCMOS) and differential (LVDS) standards were also tested in both cases.

In addition to the known single-event-functional-interrupts (SEFIs) seen in the Virtex-II, a new mode was observed in the Virtex-II Pro. This new mode is the first error type that requires a power cycle to recover and fortunately has a rather small sensitivity. We are investigating the source of this new mode and will discuss the results.


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