"Comparison of the Proton SEU Performance of the Microblaze and the Leon2 Soft Core Processor as implemented on a Xilinx Virtex-II SRAM based FPGA"

Dave M. Hiemstra, Fayez Chayab, and Kristopher Bates
MDA Space Missions

Abstract

Solutions for space applications based on a System-on-Chip (SoC) implementation that take advantage of industry standard soft-core Intellectual Properties (IPs), as compared to the conventional single board computer approach, offer benefits such as increased integration, re-configurability, and reduced mass, power, and volume, to mention a few. These benefits however come with an additional upset susceptibility in the space radiation environment. Like other SRAM based FPGAs the Virtex-II can experience upsets in their SRAM storing the logic configuration resulting in single event functionality upsets. User logic can also upset in the same manner as fixed logic. Also, upsets in the SRAM storing the logic configuration could result in internal or external I/O contentions. More over, the presence of an embedded soft-core in the system, with its software, registers, caches, and fixed logic, ands more levels of upset able elements that could fail in more spectacular modes than ever before. Therefore, SEU testing and analyses are undertaken to evaluate the performance of these systems in the space radiation environment.

In this paper, we report initial results of Single-Event Upset (SEU) tests and characterization of two industry standard soft core processors, Xilinx’s MicroBlaze and Gaisler’s Leon2, as implemented on a Virtex-II SRAM based FPGA. This report includes the dynamic SEU performance of these cores running similar reference designs. In addition, the characterization of encountered failure modes/signatures and there relationship to the architectural implementation of such soft-cores are analyzed. Finally, after presenting the radiation testing setups and methodologies that were utilized for the above tests, a set of recommendations for subsequent and future testing methodologies of such embedded cores are outlined.

 

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