"FPGA Implementation of Reduced Bit Plane Motion Estimation"
Shrutisagar Chandrasekaran, Abbes Amira, and Faycal Bensaali
Raw digital video data can consume upto 150 MBPS making video compression indispensable for efficient transmission and storage of video, with applications ranging from video on demand, HDTV, video conferencing and 3G video telephony. Block Matching (BM) algorithm is a widely used Motion Estimation (ME) technique for calculating motion vectors by minimising some cost function, typically a distortion measure such as the Sum of Absolute Differences (SAD). Optimal prediction is obtained when the Full Search (FS) algorithm is performed. However, FS is computationally intensive and requires a large number of I/O pins and large bandwidth for real time ME. An obvious and effective method for reducing the complexity of ME architecture is to reduce the number of bit planes used for computing the motion vectors. Most of the motion information is contained in the 6th bit plane, and a significant amount of motion information is also available in the 7th bit plane. The lower bit planes contain significantly less motion information, as they represent the smooth areas of the image.
In this paper, reduced bit-plane methods for ME using range reduced arithmetic units and simple Boolean operations leading to power and area efficient architectures has been presented. The proposed architectures have been simulated and synthesised on the Virtex2 FPGA series and prototyped on the Celoxica RC1000 PCI development board fitted with the Xilinx Virtex-E XCV2000E-6 FPGA. The architectures are implemented using Handel-C, a C-like language supporting parallelism, and flexible data size and provide a very powerful method of hardware implementation, which is very useful especially in custom computing applications.
Complete details of various performance metrics including power, energy, throughput rate, and PSNR, along with comparison of photometric measures with established ME techniques will be included in the full paper.
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