"Extending FPGA Verification Through The PLI"

Charlie Howard
Southwest Research Institute

Abstract:

Verilog is a hardware description language for the design of programmable logic, and is in widespread use throughout the electronics industry. It is used not only for end item design description, but also for modeling input interfaces and test stimuli during low-level verification activities. The results of this first order modeling are often then verified by visual means. There are however, significant limitations on visual verification. It is at this point that the real strength of Verilog is revealed the programming level interface (PLI).

The PLI can be used to link any type of application to the simulation, providing access to every attribute within the Verilog simulation structure under program control. The capability to read and/or modify any value in the simulation gives flexibility to perform all simulation tasks, from initializing memories at simulation start to verifying end of simulation results. C programs can be tied through the PLI to Verilog shell models, allowing C programs to be used to dynamically generate stimuli or to check design outputs. In short, the PLI allows the designer to build a robust virtual test bench that allows the functional interaction of hardware and software to first be characterized without lab space.

Using the PLI, simulations do not need to be limited in time, complexity or randomness; they can be extended as necessary to reflect the real world. Many more simulation cycles can occur, and by incorporating the capability to randomize each test, an immense number of HW/SW interactions can be characterized for flaws. Using random and directed test techniques, functional verification of the logic design can be extended far beyond that which can be provided by using first order techniques. The resulting design is much more robust and likely to function when moved into silicon.

Within the current design cycle, SWRI has extended its FPGA verification capabilities, by developing several key bus functional models and PLI routines. Specific approaches and examples will be presented.

 

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