"Highly-Scalable Reconfigurable Computing"

Roger Chamberlain1, Steven Miller2, Jason White1, and Dan Gall2

1Exegy, Inc.
2Silicon Graphics, Inc.


Reconfigurable computing, typically deployed using Field-Programmable Gate Arrays (FPGAs), is a technology that is ideally suited to exploit the fine-grained parallelism existing in many algorithms and applications. For example, if a computation can concurrently execute 100 accumulation operations, an FPGA implementation of that computation can deploy 100 adders and perform all 100 accumulation operations in parallel, all in a single chip. On the other hand, systems that include large collections of FPGAs have previously either been dedicated to specialized purposes or non-existent.

SGI is a manufacturer of large-scale, high-performance computer systems. SGI’s ccNUMA (cache coherent non-uniform memory architecture) [1] global shared memory system architecture is the basis for its general–purpose Origin and Altix HPC systems, which can scale up to thousands of compute nodes. SGI has recently developed an FPGA-based node for the NUMAlink4 interconnect that supports a 6.4 GB/s data rate into and out of the FPGA [2].

Exegy has deployed several codesigned applications onto commodity hardware (processors and FPGAs). The application focus has been on computations that involve very large (multiple terabyte) unstructured data sets [3]. On a single node, performance gains for complex text search applications exceed two orders of magnitude over software-only solutions. Other codesigned applications include encryption, signature hashing, data mining, etc. The scalability of the SGI system enables further significant performance gains on these applications.

This paper will describe our experience deploying Exegy applications on the SGI system. We will describe both the application development process as well as performance results.


  1. http://www.sgi.com/servers/altix/

  2. Steven Miller, “Requirements for Scalable Application Specific Processing in Commercial HPEC,” in Proc. of High Performance Embedded Computing Workshop, September 2004.

  3. Roger D. Chamberlain and Ron K. Cytron, “Novel Techniques for Processing Unstructured Data Sets,” in Proc. of IEEE Aerospace Conference, March 2005.


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