"Development of the Malleable Signal Processor (MSP) for the Roadrunner On-Board Processing Experiment (ROPE) on the Tacsat-2 Spacecraft"

R.L. Coxe1, G.H. Romero1, A. Pakyari1, S.D. Chang1, G.E. Galica1, J.M. Glynn1, B.D. Green1, M. Leary2, J. Lyke3, and D. Fronterhouse4

1Physical Sciences Inc.
2Newgrange Design Inc.
3
AFRL/VSSE
4
Scientific Simulations Inc.

Abstract

This paper will describe the design and development effort at Physical Sciences Inc. (PSI) of the Malleable Signal Processor (MSP), a reconfigurable computing engine equipped with five radiation-tolerant XQR2V3000 FPGAs slated for the AFRL TacSat2/Roadrunner imaging payload.  AFRL/VSSE identified PSI’s FPGA reconfigurable computing design concept, originally formulated in a Phase I Small Business Innovation Research (SBIR) program [presented at MAPLD in 2002], as a promising candidate to meet the objective of the Roadrunner On-board Processing Experiment (ROPE).   ROPE is intended to demonstrate on-board, real-time, morphable processing of multispectral imagery.  The MSP supports on-the-fly, pipelined radiometric calibration, JPEG image compression, and anomaly detection.  Additional capabilities of the MSP include rapid prototyping and on-demand functional upgrades on-orbit.  

The AFRL TacSat2 mission, currently slated for launch in summer 2006, is taking place under the aegis of the DoD Office of Force Transformation’s Responsive Space Initiative.  The stated goal of Responsive Space is to field satellite payloads in weeks and months, rather than decades.   Responsive Space represents a shift towards satellite missions that are “faster, cheaper, and good enough.”  This paper will conclude with lessons learned while developing new technology in the Brave New World of Responsive Space.

 

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