"Image 'Padding' in Limited-Memory FPGA Systems"
William F. Turri1 and Eric J. Balster2
1Systran Federal Corp.
2Air Force Research Laboratory/IFTA
This paper will discuss one specific challenge encountered when applying wavelet transforms to image data stored in the limited memory of an FPGA-based processing system.
Image compression and processing applications, originally designed for software implementation, present design challenges to engineers who wish to improve the performance of such applications with FPGA-based reconfigurable computing. One specific challenge being dealt with by Systran Federal Corp. is the problem of applying a wavelet transform along the boundary of an image stored in memory. Wavelet transforms are best implemented in hardware by using a “lifting scheme,” and such an implementation often requires the existence of data values that lie beyond the actual border of the image. Thus, rows and/or columns in the image must be “padded” or “extended” to provide the necessary data points to the wavelet transform. Zero-padding produces unacceptable distortion in the resulting (decompressed) image, but methods of periodic, odd-symmetric, and even-symmetric extension produce good results depending upon the particular wavelet in use. Such extensions are easily performed in software languages on general-purpose computers, where the image data are accessed through indexed arrays, and memory is typically more plentiful and far less expensive than with reconfigurable computing boards. Difficulties arise, however, when attempting to perform such extensions in an FPGA, where internal resources are insufficient to store large amounts of image data, and each value must be fetched from a more limited amount of external memory.
To solve this problem, Systran Federal Corp. will compare several approaches that minimize both memory usage and memory access, while seeking the maximum possible throughput. Possible solutions include the use of on-chip storage of relevant data values, using both register-based and RAM-based methods, in the form of barrel shifters, circular buffers, or FIFOs. An appropriate solution must account for the image-border challenge and perform the selected method of extension without requiring the use of additional memory locations to store the extended values, and without requiring redundant memory access. The solution should incur the least amount of overhead possible, both in resource (gate) consumption and over-all performance.
The paper will present the results of the comparison between the various methods just mentioned, showing that the final solution is memory-efficient in general, and specifically when dealing with data extension. Engineers will continue to encounter this challenge as they design hardware solutions for increasingly complex image compression and processing applications that require increasingly large images. The images being dealt with by Systran Federal Corp. are complex (magnitude/phase) representations of raw Synthetic Aperture Radar (SAR) data, but the technique developed should be applicable to a variety of image types. A Xilinx Virtex-II Pro FPGA is the targeted device, and it is implemented as part of a Nallatech BenNUEY-PCI-4E reconfigurable computing board.
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