"FPGA Development for High Altitude Subsonic Parachute Testing"

James E.Kowalski, Konstantin G. Gromov and Edward H. Konefat
Jet Propulsion Laboratory, California Institute of Technology

Abstract

This paper describes a rapid, top down requirements-driven design of an FPGA used in an Earth qualification test program for a new Mars subsonic parachute.  The FPGA is used to process and control storage of telemetry data from multiple sensors throughout launch, ascent, deployment and descent phases of the subsonic parachute test.

 The FPGA used was a Xilinx Virtex-E, embedded on a COTS PCMCIA card with dual SRAM buffers.  Software on a SBC reads filled SRAM using Direct Memory Access (DMA), and stores the data in a flash disk.

The FPGA design is guided by a spreadsheet of memory partitions based on data rates from each sensor.  Accumulators are used to compress some of the high rate data.  A prioritized queue is used to control the servicing of received data from multiple sources.  The memory transfer rate is high enough to allow single depth buffering.

Section I. covers requirements. Section II details methodology. Section III presents implementation results including functional verification, resource utilization, and timing.

Data post processing and reformatting is in Section IV. Section V describes some of the test results.

 

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